1* Freescale enhanced Direct Memory Access(eDMA) Controller 2 3 The eDMA channels have multiplex capability by programmble memory-mapped 4registers. channels are split into two groups, called DMAMUX0 and DMAMUX1, 5specific DMA request source can only be multiplexed by any channel of certain 6group, DMAMUX0 or DMAMUX1, but not both. 7 8* eDMA Controller 9Required properties: 10- compatible : 11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC 12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp 13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the 14 LS1028A SoC. 15- reg : Specifies base physical address(s) and size of the eDMA registers. 16 The 1st region is eDMA control register's address and size. 17 The 2nd and the 3rd regions are programmable channel multiplexing 18 control register's address and size. 19- interrupts : A list of interrupt-specifiers, one for each entry in 20 interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel 21 per transmission interrupt, total 16 channel interrupt and 1 22 error interrupt(located in the last), no interrupt-names list on 23 i.mx7ulp for clean on dts. 24- #dma-cells : Must be <2>. 25 The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1). 26 Specific request source can only be multiplexed by specific channels 27 group called DMAMUX. 28 The 2nd cell specifies the request source(slot) ID. 29 See the SoC's reference manual for all the supported request sources. 30- dma-channels : Number of channels supported by the controller 31- clock-names : A list of channel group clock names. Should contain: 32 "dmamux0" - clock name of mux0 group 33 "dmamux1" - clock name of mux1 group 34 Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp. 35- clocks : A list of phandle and clock-specifier pairs, one for each entry in 36 clock-names. 37 38Optional properties: 39- big-endian: If present registers and hardware scatter/gather descriptors 40 of the eDMA are implemented in big endian mode, otherwise in little 41 mode. 42- interrupt-names : Should contain the below on vf610 similar SoC but not used 43 on i.mx7ulp similar SoC: 44 "edma-tx" - the transmission interrupt 45 "edma-err" - the error interrupt 46 47 48Examples: 49 50edma0: dma-controller@40018000 { 51 #dma-cells = <2>; 52 compatible = "fsl,vf610-edma"; 53 reg = <0x40018000 0x2000>, 54 <0x40024000 0x1000>, 55 <0x40025000 0x1000>; 56 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 57 <0 9 IRQ_TYPE_LEVEL_HIGH>; 58 interrupt-names = "edma-tx", "edma-err"; 59 dma-channels = <32>; 60 clock-names = "dmamux0", "dmamux1"; 61 clocks = <&clks VF610_CLK_DMAMUX0>, 62 <&clks VF610_CLK_DMAMUX1>; 63}; /* vf610 */ 64 65edma1: dma-controller@40080000 { 66 #dma-cells = <2>; 67 compatible = "fsl,imx7ulp-edma"; 68 reg = <0x40080000 0x2000>, 69 <0x40210000 0x1000>; 70 dma-channels = <32>; 71 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 87 /* last is eDMA2-ERR interrupt */ 88 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 89 clock-names = "dma", "dmamux0"; 90 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, 91 <&pcc2 IMX7ULP_CLK_DMA_MUX1>; 92}; /* i.mx7ulp */ 93 94* DMA clients 95DMA client drivers that uses the DMA function must use the format described 96in the dma.txt file, using a two-cell specifier for each channel: the 1st 97specifies the channel group(DMAMUX) in which this request can be multiplexed, 98and the 2nd specifies the request source. 99 100Examples: 101 102sai2: sai@40031000 { 103 compatible = "fsl,vf610-sai"; 104 reg = <0x40031000 0x1000>; 105 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 106 clock-names = "sai"; 107 clocks = <&clks VF610_CLK_SAI2>; 108 dma-names = "tx", "rx"; 109 dmas = <&edma0 0 21>, 110 <&edma0 0 20>; 111}; 112