1* Atmel Extensible Direct Memory Access Controller (XDMAC) 2 3* XDMA Controller 4Required properties: 5- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or 6 "microchip,sama7g5-dma". 7- reg: Should contain DMA registers location and length. 8- interrupts: Should contain DMA interrupt. 9- #dma-cells: Must be <1>, used to represent the number of integer cells in 10the dmas property of client devices. 11 - The 1st cell specifies the channel configuration register: 12 - bit 13: SIF, source interface identifier, used to get the memory 13 interface identifier, 14 - bit 14: DIF, destination interface identifier, used to get the peripheral 15 interface identifier, 16 - bit 30-24: PERID, peripheral identifier. 17 18Example: 19 20dma1: dma-controller@f0004000 { 21 compatible = "atmel,sama5d4-dma"; 22 reg = <0xf0004000 0x200>; 23 interrupts = <50 4 0>; 24 #dma-cells = <1>; 25}; 26 27 28* DMA clients 29DMA clients connected to the Atmel XDMA controller must use the format 30described in the dma.txt file, using a one-cell specifier for each channel. 31The two cells in order are: 321. A phandle pointing to the DMA controller. 332. Channel configuration register. Configurable fields are: 34 - bit 13: SIF, source interface identifier, used to get the memory 35 interface identifier, 36 - bit 14: DIF, destination interface identifier, used to get the peripheral 37 interface identifier, 38 - bit 30-24: PERID, peripheral identifier. 39 40Example: 41 42i2c2: i2c@f8024000 { 43 compatible = "atmel,at91sam9x5-i2c"; 44 reg = <0xf8024000 0x4000>; 45 interrupts = <34 4 6>; 46 dmas = <&dma1 47 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 48 | AT91_XDMAC_DT_PERID(6))>, 49 <&dma1 50 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 51 | AT91_XDMAC_DT_PERID(7))>; 52 dma-names = "tx", "rx"; 53}; 54