1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Altera mSGDMA IP core 8 9maintainers: 10 - Olivier Dautricourt <olivierdautricourt@gmail.com> 11 12description: | 13 Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) 14 intellectual property (IP) 15 16allOf: 17 - $ref: dma-controller.yaml# 18 19properties: 20 compatible: 21 const: altr,socfpga-msgdma 22 23 reg: 24 items: 25 - description: Control and Status Register Slave Port 26 - description: Descriptor Slave Port 27 - description: Response Slave Port (Optional) 28 minItems: 2 29 30 reg-names: 31 items: 32 - const: csr 33 - const: desc 34 - const: resp 35 minItems: 2 36 37 interrupts: 38 maxItems: 1 39 40 "#dma-cells": 41 const: 1 42 description: 43 The cell identifies the channel id (must be 0) 44 45required: 46 - compatible 47 - reg 48 - reg-names 49 - interrupts 50 51unevaluatedProperties: false 52 53examples: 54 - | 55 #include <dt-bindings/interrupt-controller/irq.h> 56 57 msgdma_controller: dma-controller@ff200b00 { 58 compatible = "altr,socfpga-msgdma"; 59 reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>; 60 reg-names = "csr", "desc", "resp"; 61 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 62 #dma-cells = <1>; 63 }; 64