xref: /freebsd/sys/contrib/device-tree/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml (revision 77013d11e6483b970af25e13c9b892075742f7e5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx ZynqMP DisplayPort Subsystem
8
9description: |
10  The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11  implements the display and audio pipelines based on the DisplayPort v1.2
12  standard. The subsystem includes multiple functional blocks as below:
13
14               +------------------------------------------------------------+
15  +--------+   | +----------------+     +-----------+                       |
16  | DPDMA  | --->|                | --> |   Video   | Video +-------------+ |
17  | 4x vid |   | |                |     | Rendering | -+--> |             | |   +------+
18  | 2x aud |   | |  Audio/Video   | --> | Pipeline  |  |    | DisplayPort |---> | PHY0 |
19  +--------+   | | Buffer Manager |     +-----------+  |    |   Source    | |   +------+
20               | |    and STC     |     +-----------+  |    | Controller  | |   +------+
21  Live Video --->|                | --> |   Audio   | Audio |             |---> | PHY1 |
22               | |                |     |   Mixer   | --+-> |             | |   +------+
23  Live Audio --->|                | --> |           |  ||   +-------------+ |
24               | +----------------+     +-----------+  ||                   |
25               +---------------------------------------||-------------------+
26                                                       vv
27                                                 Blended Video and
28                                                 Mixed Audio to PL
29
30  The Buffer Manager interacts with external interface such as DMA engines or
31  live audio/video streams from the programmable logic. The Video Rendering
32  Pipeline blends the video and graphics layers and performs colorspace
33  conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34  Source Controller handles the DisplayPort protocol and connects to external
35  PHYs.
36
37  The subsystem supports 2 video and 2 audio streams, and various pixel formats
38  and depths up to 4K@30 resolution.
39
40  Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41  (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
42  for more details.
43
44maintainers:
45  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
46
47properties:
48  compatible:
49    const: xlnx,zynqmp-dpsub-1.7
50
51  reg:
52    maxItems: 4
53  reg-names:
54    items:
55      - const: dp
56      - const: blend
57      - const: av_buf
58      - const: aud
59
60  interrupts:
61    maxItems: 1
62
63  clocks:
64    description:
65      The APB clock and at least one video clock are mandatory, the audio clock
66      is optional.
67    minItems: 2
68    maxItems: 4
69    items:
70      - description: dp_apb_clk is the APB clock
71      - description: dp_aud_clk is the Audio clock
72      - description:
73          dp_vtc_pixel_clk_in is the non-live video clock (from Processing
74          System)
75      - description:
76          dp_live_video_in_clk is the live video clock (from Programmable
77          Logic)
78  clock-names:
79    oneOf:
80      - minItems: 2
81        maxItems: 3
82        items:
83          - const: dp_apb_clk
84          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
85          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
86      - minItems: 3
87        maxItems: 4
88        items:
89          - const: dp_apb_clk
90          - const: dp_aud_clk
91          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
92          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
93
94  power-domains:
95    maxItems: 1
96
97  resets:
98    maxItems: 1
99
100  dmas:
101    items:
102      - description: Video layer, plane 0 (RGB or luma)
103      - description: Video layer, plane 1 (U/V or U)
104      - description: Video layer, plane 2 (V)
105      - description: Graphics layer
106  dma-names:
107    items:
108      - const: vid0
109      - const: vid1
110      - const: vid2
111      - const: gfx0
112
113  phys:
114    description: PHYs for the DP data lanes
115    minItems: 1
116    maxItems: 2
117  phy-names:
118    minItems: 1
119    maxItems: 2
120    items:
121      - const: dp-phy0
122      - const: dp-phy1
123
124required:
125  - compatible
126  - reg
127  - reg-names
128  - interrupts
129  - clocks
130  - clock-names
131  - power-domains
132  - resets
133  - dmas
134  - dma-names
135  - phys
136  - phy-names
137
138additionalProperties: false
139
140examples:
141  - |
142    #include <dt-bindings/phy/phy.h>
143    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
144
145    display@fd4a0000 {
146        compatible = "xlnx,zynqmp-dpsub-1.7";
147        reg = <0xfd4a0000 0x1000>,
148              <0xfd4aa000 0x1000>,
149              <0xfd4ab000 0x1000>,
150              <0xfd4ac000 0x1000>;
151        reg-names = "dp", "blend", "av_buf", "aud";
152        interrupts = <0 119 4>;
153        interrupt-parent = <&gic>;
154
155        clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
156        clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
157
158        power-domains = <&pd_dp>;
159        resets = <&reset ZYNQMP_RESET_DP>;
160
161        dma-names = "vid0", "vid1", "vid2", "gfx0";
162        dmas = <&xlnx_dpdma 0>,
163               <&xlnx_dpdma 1>,
164               <&xlnx_dpdma 2>,
165               <&xlnx_dpdma 3>;
166
167        phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,
168               <&psgtr 0 PHY_TYPE_DP 1 3 27000000>;
169
170        phy-names = "dp-phy0", "dp-phy1";
171    };
172
173...
174