xref: /freebsd/sys/contrib/device-tree/Bindings/display/ti/ti,am65x-dss.yaml (revision 397e83df75e0fcd0d3fcb95ae4d794cb7600fc89) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Texas Instruments AM65x Display Subsystem
9
10maintainers:
11  - Jyri Sarha <jsarha@ti.com>
12  - Tomi Valkeinen <tomi.valkeinen@ti.com>
13
14description: |
15  The AM625 and AM65x TI Keystone Display SubSystem with two output
16  ports and two video planes. In AM65x DSS, the first video port
17  supports 1 OLDI TX and in AM625 DSS, the first video port output is
18  internally routed to 2 OLDI TXes. The second video port supports DPI
19  format. The first plane is full video plane with all features and the
20  second is a "lite plane" without scaling support.
21
22properties:
23  compatible:
24    enum:
25      - ti,am625-dss
26      - ti,am62a7,dss
27      - ti,am65x-dss
28
29  reg:
30    description:
31      Addresses to each DSS memory region described in the SoC's TRM.
32    items:
33      - description: common DSS register area
34      - description: VIDL1 light video plane
35      - description: VID video plane
36      - description: OVR1 overlay manager for vp1
37      - description: OVR2 overlay manager for vp2
38      - description: VP1 video port 1
39      - description: VP2 video port 2
40
41  reg-names:
42    items:
43      - const: common
44      - const: vidl1
45      - const: vid
46      - const: ovr1
47      - const: ovr2
48      - const: vp1
49      - const: vp2
50
51  clocks:
52    items:
53      - description: fck DSS functional clock
54      - description: vp1 Video Port 1 pixel clock
55      - description: vp2 Video Port 2 pixel clock
56
57  clock-names:
58    items:
59      - const: fck
60      - const: vp1
61      - const: vp2
62
63  assigned-clocks:
64    minItems: 1
65    maxItems: 3
66
67  assigned-clock-parents:
68    minItems: 1
69    maxItems: 3
70
71  interrupts:
72    maxItems: 1
73
74  power-domains:
75    maxItems: 1
76    description: phandle to the associated power domain
77
78  dma-coherent:
79    type: boolean
80
81  ports:
82    $ref: /schemas/graph.yaml#/properties/ports
83
84    properties:
85      port@0:
86        $ref: /schemas/graph.yaml#/properties/port
87        description:
88          For AM65x DSS, the OLDI output port node from video port 1.
89          For AM625 DSS, the internal DPI output port node from video
90          port 1.
91          For AM62A7 DSS, the port is tied off inside the SoC.
92
93      port@1:
94        $ref: /schemas/graph.yaml#/properties/port
95        description:
96          The DSS DPI output port node from video port 2
97
98  ti,am65x-oldi-io-ctrl:
99    $ref: /schemas/types.yaml#/definitions/phandle
100    description:
101      phandle to syscon device node mapping OLDI IO_CTRL registers.
102      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
103      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
104      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
105      interface to work.
106
107  max-memory-bandwidth:
108    $ref: /schemas/types.yaml#/definitions/uint32
109    description:
110      Input memory (from main memory to dispc) bandwidth limit in
111      bytes per second
112
113allOf:
114  - if:
115      properties:
116        compatible:
117          contains:
118            const: ti,am62a7-dss
119    then:
120      properties:
121        ports:
122          properties:
123            port@0: false
124
125required:
126  - compatible
127  - reg
128  - reg-names
129  - clocks
130  - clock-names
131  - interrupts
132  - ports
133
134additionalProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/interrupt-controller/arm-gic.h>
139    #include <dt-bindings/interrupt-controller/irq.h>
140    #include <dt-bindings/soc/ti,sci_pm_domain.h>
141
142    dss: dss@4a00000 {
143            compatible = "ti,am65x-dss";
144            reg =   <0x04a00000 0x1000>, /* common */
145                    <0x04a02000 0x1000>, /* vidl1 */
146                    <0x04a06000 0x1000>, /* vid */
147                    <0x04a07000 0x1000>, /* ovr1 */
148                    <0x04a08000 0x1000>, /* ovr2 */
149                    <0x04a0a000 0x1000>, /* vp1 */
150                    <0x04a0b000 0x1000>; /* vp2 */
151            reg-names = "common", "vidl1", "vid",
152                    "ovr1", "ovr2", "vp1", "vp2";
153            ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
154            power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
155            clocks =        <&k3_clks 67 1>,
156                            <&k3_clks 216 1>,
157                            <&k3_clks 67 2>;
158            clock-names = "fck", "vp1", "vp2";
159            interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
160            ports {
161                    #address-cells = <1>;
162                    #size-cells = <0>;
163                    port@0 {
164                            reg = <0>;
165                            oldi_out0: endpoint {
166                                    remote-endpoint = <&lcd_in0>;
167                            };
168                    };
169            };
170    };
171