xref: /freebsd/sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra20-vi.yaml (revision b59017c5cad90d0f09a59e68c00457b7faf93e7c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Video Input controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^vi@[0-9a-f]+$"
16
17  compatible:
18    oneOf:
19      - const: nvidia,tegra20-vi
20      - const: nvidia,tegra30-vi
21      - const: nvidia,tegra114-vi
22      - const: nvidia,tegra124-vi
23      - items:
24          - const: nvidia,tegra132-vi
25          - const: nvidia,tegra124-vi
26      - const: nvidia,tegra210-vi
27      - const: nvidia,tegra186-vi
28      - const: nvidia,tegra194-vi
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  resets:
40    items:
41      - description: module reset
42
43  reset-names:
44    items:
45      - const: vi
46
47  iommus:
48    maxItems: 1
49
50  interconnects:
51    minItems: 4
52    maxItems: 5
53
54  interconnect-names:
55    minItems: 4
56    maxItems: 5
57
58  operating-points-v2: true
59
60  power-domains:
61    items:
62      - description: phandle to the VENC power domain
63
64  "#address-cells":
65    const: 1
66
67  "#size-cells":
68    const: 1
69
70  ranges:
71    maxItems: 1
72
73  avdd-dsi-csi-supply:
74    description: DSI/CSI power supply. Must supply 1.2 V.
75
76  vip:
77    $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml
78
79  ports:
80    $ref: /schemas/graph.yaml#/properties/ports
81
82    properties:
83      port@0:
84        $ref: /schemas/graph.yaml#/properties/port
85        description:
86          Input from the VIP (parallel input capture) module
87
88patternProperties:
89  "^csi@[0-9a-f]+$":
90    type: object
91
92additionalProperties: false
93
94required:
95  - compatible
96  - reg
97  - interrupts
98  - clocks
99
100allOf:
101  - if:
102      properties:
103        compatible:
104          contains:
105            enum:
106              - nvidia,tegra20-vi
107              - nvidia,tegra30-vi
108              - nvidia,tegra114-vi
109              - nvidia,tegra124-vi
110    then:
111      required:
112        - resets
113        - reset-names
114    else:
115      required:
116        - power-domains
117
118examples:
119  - |
120    #include <dt-bindings/clock/tegra20-car.h>
121    #include <dt-bindings/interrupt-controller/arm-gic.h>
122
123    i2c {
124        #address-cells = <1>;
125        #size-cells = <0>;
126        camera@48 {
127            compatible = "aptina,mt9v111";
128            reg = <0x48>;
129            clocks = <&camera_clk>;
130
131            port {
132                mt9v111_out: endpoint {
133                    remote-endpoint = <&vi_vip_in>;
134                };
135            };
136        };
137    };
138
139    vi@54080000 {
140        compatible = "nvidia,tegra20-vi";
141        reg = <0x54080000 0x00040000>;
142        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143        clocks = <&tegra_car TEGRA20_CLK_VI>;
144        resets = <&tegra_car 100>;
145        reset-names = "vi";
146
147        vip {
148            compatible = "nvidia,tegra20-vip";
149            ports {
150                #address-cells = <1>;
151                #size-cells = <0>;
152                port@0 {
153                    reg = <0>;
154                    vi_vip_in: endpoint {
155                        remote-endpoint = <&mt9v111_out>;
156                    };
157                };
158                port@1 {
159                    reg = <1>;
160                    vi_vip_out: endpoint {
161                        remote-endpoint = <&vi_in>;
162                    };
163                };
164            };
165        };
166
167        ports {
168            #address-cells = <1>;
169            #size-cells = <0>;
170            port@0 {
171                reg = <0>;
172                vi_in: endpoint {
173                    remote-endpoint = <&vi_vip_out>;
174                };
175            };
176        };
177    };
178
179  - |
180    #include <dt-bindings/clock/tegra210-car.h>
181    #include <dt-bindings/interrupt-controller/arm-gic.h>
182
183    vi@54080000 {
184        compatible = "nvidia,tegra210-vi";
185        reg = <0x54080000 0x00000700>;
186        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
187        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
188        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
189
190        clocks = <&tegra_car TEGRA210_CLK_VI>;
191        power-domains = <&pd_venc>;
192
193        #address-cells = <1>;
194        #size-cells = <1>;
195
196        ranges = <0x0 0x54080000 0x2000>;
197
198        csi@838 {
199            compatible = "nvidia,tegra210-csi";
200            reg = <0x838 0x1300>;
201            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
202                              <&tegra_car TEGRA210_CLK_CILCD>,
203                              <&tegra_car TEGRA210_CLK_CILE>,
204                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
205            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
206                                     <&tegra_car TEGRA210_CLK_PLL_P>,
207                                     <&tegra_car TEGRA210_CLK_PLL_P>;
208            assigned-clock-rates = <102000000>,
209                                   <102000000>,
210                                   <102000000>,
211                                   <972000000>;
212
213            clocks = <&tegra_car TEGRA210_CLK_CSI>,
214                     <&tegra_car TEGRA210_CLK_CILAB>,
215                     <&tegra_car TEGRA210_CLK_CILCD>,
216                     <&tegra_car TEGRA210_CLK_CILE>,
217                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
218            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
219            power-domains = <&pd_sor>;
220        };
221    };
222