xref: /freebsd/sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra20-vi.yaml (revision 370e009188ba90c3290b1479aa06ec98b66e140a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Video Input controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^vi@[0-9a-f]+$"
16
17  compatible:
18    oneOf:
19      - const: nvidia,tegra20-vi
20      - const: nvidia,tegra30-vi
21      - const: nvidia,tegra114-vi
22      - const: nvidia,tegra124-vi
23      - items:
24          - const: nvidia,tegra132-vi
25          - const: nvidia,tegra124-vi
26      - const: nvidia,tegra210-vi
27      - const: nvidia,tegra186-vi
28      - const: nvidia,tegra194-vi
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  resets:
40    items:
41      - description: module reset
42
43  reset-names:
44    items:
45      - const: vi
46
47  iommus:
48    maxItems: 1
49
50  interconnects:
51    minItems: 4
52    maxItems: 5
53
54  interconnect-names:
55    minItems: 4
56    maxItems: 5
57
58  operating-points-v2:
59    $ref: "/schemas/types.yaml#/definitions/phandle"
60
61  power-domains:
62    items:
63      - description: phandle to the VENC power domain
64
65  "#address-cells":
66    const: 1
67
68  "#size-cells":
69    const: 1
70
71  ranges:
72    maxItems: 1
73
74  avdd-dsi-csi-supply:
75    description: DSI/CSI power supply. Must supply 1.2 V.
76
77patternProperties:
78  "^csi@[0-9a-f]+$":
79    type: object
80
81additionalProperties: false
82
83required:
84  - compatible
85  - reg
86  - interrupts
87  - clocks
88
89allOf:
90  - if:
91      properties:
92        compatible:
93          contains:
94            enum:
95              - nvidia,tegra20-vi
96              - nvidia,tegra30-vi
97              - nvidia,tegra114-vi
98              - nvidia,tegra124-vi
99    then:
100      required:
101        - resets
102        - reset-names
103    else:
104      required:
105        - power-domains
106
107examples:
108  - |
109    #include <dt-bindings/clock/tegra20-car.h>
110    #include <dt-bindings/interrupt-controller/arm-gic.h>
111
112    vi@54080000 {
113        compatible = "nvidia,tegra20-vi";
114        reg = <0x54080000 0x00040000>;
115        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
116        clocks = <&tegra_car TEGRA20_CLK_VI>;
117        resets = <&tegra_car 100>;
118        reset-names = "vi";
119    };
120
121  - |
122    #include <dt-bindings/clock/tegra210-car.h>
123    #include <dt-bindings/interrupt-controller/arm-gic.h>
124
125    vi@54080000 {
126        compatible = "nvidia,tegra210-vi";
127        reg = <0x54080000 0x00000700>;
128        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
129        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
130        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
131
132        clocks = <&tegra_car TEGRA210_CLK_VI>;
133        power-domains = <&pd_venc>;
134
135        #address-cells = <1>;
136        #size-cells = <1>;
137
138        ranges = <0x0 0x54080000 0x2000>;
139
140        csi@838 {
141            compatible = "nvidia,tegra210-csi";
142            reg = <0x838 0x1300>;
143            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
144                              <&tegra_car TEGRA210_CLK_CILCD>,
145                              <&tegra_car TEGRA210_CLK_CILE>,
146                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
147            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
148                                     <&tegra_car TEGRA210_CLK_PLL_P>,
149                                     <&tegra_car TEGRA210_CLK_PLL_P>;
150            assigned-clock-rates = <102000000>,
151                                   <102000000>,
152                                   <102000000>,
153                                   <972000000>;
154
155            clocks = <&tegra_car TEGRA210_CLK_CSI>,
156                     <&tegra_car TEGRA210_CLK_CILAB>,
157                     <&tegra_car TEGRA210_CLK_CILCD>,
158                     <&tegra_car TEGRA210_CLK_CILE>,
159                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
160            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
161            power-domains = <&pd_sor>;
162        };
163    };
164