xref: /freebsd/sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra20-vi.yaml (revision 031beb4e239bfce798af17f5fe8dba8bcaf13d99) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Video Input controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14  $nodename:
15    pattern: "^vi@[0-9a-f]+$"
16
17  compatible:
18    oneOf:
19      - const: nvidia,tegra20-vi
20      - const: nvidia,tegra30-vi
21      - const: nvidia,tegra114-vi
22      - const: nvidia,tegra124-vi
23      - items:
24          - const: nvidia,tegra132-vi
25          - const: nvidia,tegra124-vi
26      - const: nvidia,tegra210-vi
27      - const: nvidia,tegra186-vi
28      - const: nvidia,tegra194-vi
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  resets:
40    items:
41      - description: module reset
42
43  reset-names:
44    items:
45      - const: vi
46
47  iommus:
48    maxItems: 1
49
50  interconnects:
51    minItems: 4
52    maxItems: 5
53
54  interconnect-names:
55    minItems: 4
56    maxItems: 5
57
58  operating-points-v2: true
59
60  power-domains:
61    items:
62      - description: phandle to the VENC power domain
63
64  "#address-cells":
65    const: 1
66
67  "#size-cells":
68    const: 1
69
70  ranges:
71    maxItems: 1
72
73  avdd-dsi-csi-supply:
74    description: DSI/CSI power supply. Must supply 1.2 V.
75
76patternProperties:
77  "^csi@[0-9a-f]+$":
78    type: object
79
80additionalProperties: false
81
82required:
83  - compatible
84  - reg
85  - interrupts
86  - clocks
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - nvidia,tegra20-vi
95              - nvidia,tegra30-vi
96              - nvidia,tegra114-vi
97              - nvidia,tegra124-vi
98    then:
99      required:
100        - resets
101        - reset-names
102    else:
103      required:
104        - power-domains
105
106examples:
107  - |
108    #include <dt-bindings/clock/tegra20-car.h>
109    #include <dt-bindings/interrupt-controller/arm-gic.h>
110
111    vi@54080000 {
112        compatible = "nvidia,tegra20-vi";
113        reg = <0x54080000 0x00040000>;
114        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
115        clocks = <&tegra_car TEGRA20_CLK_VI>;
116        resets = <&tegra_car 100>;
117        reset-names = "vi";
118    };
119
120  - |
121    #include <dt-bindings/clock/tegra210-car.h>
122    #include <dt-bindings/interrupt-controller/arm-gic.h>
123
124    vi@54080000 {
125        compatible = "nvidia,tegra210-vi";
126        reg = <0x54080000 0x00000700>;
127        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
128        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
129        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
130
131        clocks = <&tegra_car TEGRA210_CLK_VI>;
132        power-domains = <&pd_venc>;
133
134        #address-cells = <1>;
135        #size-cells = <1>;
136
137        ranges = <0x0 0x54080000 0x2000>;
138
139        csi@838 {
140            compatible = "nvidia,tegra210-csi";
141            reg = <0x838 0x1300>;
142            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
143                              <&tegra_car TEGRA210_CLK_CILCD>,
144                              <&tegra_car TEGRA210_CLK_CILE>,
145                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
146            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
147                                     <&tegra_car TEGRA210_CLK_PLL_P>,
148                                     <&tegra_car TEGRA210_CLK_PLL_P>;
149            assigned-clock-rates = <102000000>,
150                                   <102000000>,
151                                   <102000000>,
152                                   <972000000>;
153
154            clocks = <&tegra_car TEGRA210_CLK_CSI>,
155                     <&tegra_car TEGRA210_CLK_CILAB>,
156                     <&tegra_car TEGRA210_CLK_CILCD>,
157                     <&tegra_car TEGRA210_CLK_CILE>,
158                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
159            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
160            power-domains = <&pd_sor>;
161        };
162    };
163