xref: /freebsd/sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra20-host1x.yaml (revision b077aed33b7b6aefca7b17ddb250cf521f938613) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra host1x controller
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: The host1x top-level node defines a number of children, each
14  representing one of the host1x client modules defined in this binding.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - nvidia,tegra20-host1x
21          - nvidia,tegra30-host1x
22          - nvidia,tegra114-host1x
23          - nvidia,tegra124-host1x
24          - nvidia,tegra210-host1x
25          - nvidia,tegra186-host1x
26          - nvidia,tegra194-host1x
27          - nvidia,tegra234-host1x
28
29      - items:
30          - const: nvidia,tegra132-host1x
31          - const: nvidia,tegra124-host1x
32
33  reg:
34    minItems: 1
35    maxItems: 3
36
37  reg-names:
38    minItems: 1
39    maxItems: 3
40
41  interrupts:
42    minItems: 1
43    maxItems: 9
44
45  interrupt-names:
46    minItems: 1
47    maxItems: 9
48
49  '#address-cells':
50    description: The number of cells used to represent physical base addresses
51      in the host1x address space.
52    enum: [1, 2]
53
54  '#size-cells':
55    description: The number of cells used to represent the size of an address
56      range in the host1x address space.
57    enum: [1, 2]
58
59  ranges:
60    maxItems: 1
61
62  clocks:
63    description: Must contain one entry, for the module clock. See
64      ../clocks/clock-bindings.txt for details.
65
66  clock-names:
67    items:
68      - const: host1x
69
70  resets:
71    minItems: 1 # MC reset is optional on Tegra186 and later
72    items:
73      - description: module reset
74      - description: memory client hotflush reset
75
76  reset-names:
77    minItems: 1 # MC reset is optional on Tegra186 and later
78    items:
79      - const: host1x
80      - const: mc
81
82  iommus:
83    maxItems: 1
84
85  interconnects:
86    items:
87      - description: memory read client for host1x
88
89  interconnect-names:
90    items:
91      - const: dma-mem # read
92
93  operating-points-v2:
94    $ref: "/schemas/types.yaml#/definitions/phandle"
95
96  power-domains:
97    items:
98      - description: phandle to the HEG or core power domain
99
100required:
101  - compatible
102  - interrupts
103  - interrupt-names
104  - '#address-cells'
105  - '#size-cells'
106  - ranges
107  - reg
108  - clocks
109  - clock-names
110
111unevaluatedProperties:
112  type: object
113
114allOf:
115  - if:
116      properties:
117        compatible:
118          contains:
119            enum:
120              - nvidia,tegra20-host1x
121              - nvidia,tegra30-host1x
122              - nvidia,tegra114-host1x
123              - nvidia,tegra124-host1x
124              - nvidia,tegra210-host1x
125    then:
126      properties:
127        interrupts:
128          items:
129            - description: host1x syncpoint interrupt
130            - description: host1x general interrupt
131
132        interrupt-names:
133          items:
134            - const: syncpt
135            - const: host1x
136      required:
137        - resets
138        - reset-names
139  - if:
140      properties:
141        compatible:
142          contains:
143            enum:
144              - nvidia,tegra186-host1x
145              - nvidia,tegra194-host1x
146    then:
147      properties:
148        reg-names:
149          items:
150            - const: hypervisor
151            - const: vm
152
153        reg:
154          items:
155            - description: region used by the hypervisor
156            - description: region assigned to the virtual machine
157
158        resets:
159          maxItems: 1
160
161        reset-names:
162          maxItems: 1
163
164        interrupts:
165          items:
166            - description: host1x syncpoint interrupt
167            - description: host1x general interrupt
168
169        interrupt-names:
170          items:
171            - const: syncpt
172            - const: host1x
173
174        iommu-map:
175          description: Specification of stream IDs available for memory context device
176            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
177            usable stream IDs.
178
179      required:
180        - reg-names
181  - if:
182      properties:
183        compatible:
184          contains:
185            enum:
186              - nvidia,tegra234-host1x
187    then:
188      properties:
189        reg-names:
190          items:
191            - const: common
192            - const: hypervisor
193            - const: vm
194
195        reg:
196          items:
197            - description: region used by host1x server
198            - description: region used by the hypervisor
199            - description: region assigned to the virtual machine
200
201        interrupts:
202          items:
203            - description: host1x syncpoint interrupt 0
204            - description: host1x syncpoint interrupt 1
205            - description: host1x syncpoint interrupt 2
206            - description: host1x syncpoint interrupt 3
207            - description: host1x syncpoint interrupt 4
208            - description: host1x syncpoint interrupt 5
209            - description: host1x syncpoint interrupt 6
210            - description: host1x syncpoint interrupt 7
211            - description: host1x general interrupt
212
213        interrupt-names:
214          items:
215            - const: syncpt0
216            - const: syncpt1
217            - const: syncpt2
218            - const: syncpt3
219            - const: syncpt4
220            - const: syncpt5
221            - const: syncpt6
222            - const: syncpt7
223            - const: host1x
224
225        iommu-map:
226          description: Specification of stream IDs available for memory context device
227            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
228            usable stream IDs.
229
230      required:
231        - reg-names
232
233examples:
234  - |
235    #include <dt-bindings/clock/tegra20-car.h>
236    #include <dt-bindings/gpio/tegra-gpio.h>
237    #include <dt-bindings/memory/tegra20-mc.h>
238
239    host1x@50000000 {
240        compatible = "nvidia,tegra20-host1x";
241        reg = <0x50000000 0x00024000>;
242        interrupts = <0 65 0x04>, /* mpcore syncpt */
243                     <0 67 0x04>; /* mpcore general */
244        interrupt-names = "syncpt", "host1x";
245        clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
246        clock-names = "host1x";
247        resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
248        reset-names = "host1x", "mc";
249
250        #address-cells = <1>;
251        #size-cells = <1>;
252
253        ranges = <0x54000000 0x54000000 0x04000000>;
254
255        mpe@54040000 {
256            compatible = "nvidia,tegra20-mpe";
257            reg = <0x54040000 0x00040000>;
258            interrupts = <0 68 0x04>;
259            clocks = <&tegra_car TEGRA20_CLK_MPE>;
260            resets = <&tegra_car 60>;
261            reset-names = "mpe";
262        };
263
264        vi@54080000 {
265            compatible = "nvidia,tegra20-vi";
266            reg = <0x54080000 0x00040000>;
267            interrupts = <0 69 0x04>;
268            clocks = <&tegra_car TEGRA20_CLK_VI>;
269            resets = <&tegra_car 100>;
270            reset-names = "vi";
271        };
272
273        epp@540c0000 {
274            compatible = "nvidia,tegra20-epp";
275            reg = <0x540c0000 0x00040000>;
276            interrupts = <0 70 0x04>;
277            clocks = <&tegra_car TEGRA20_CLK_EPP>;
278            resets = <&tegra_car 19>;
279            reset-names = "epp";
280        };
281
282        isp@54100000 {
283            compatible = "nvidia,tegra20-isp";
284            reg = <0x54100000 0x00040000>;
285            interrupts = <0 71 0x04>;
286            clocks = <&tegra_car TEGRA20_CLK_ISP>;
287            resets = <&tegra_car 23>;
288            reset-names = "isp";
289        };
290
291        gr2d@54140000 {
292            compatible = "nvidia,tegra20-gr2d";
293            reg = <0x54140000 0x00040000>;
294            interrupts = <0 72 0x04>;
295            clocks = <&tegra_car TEGRA20_CLK_GR2D>;
296            resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
297            reset-names = "2d", "mc";
298        };
299
300        gr3d@54180000 {
301            compatible = "nvidia,tegra20-gr3d";
302            reg = <0x54180000 0x00040000>;
303            clocks = <&tegra_car TEGRA20_CLK_GR3D>;
304            resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
305            reset-names = "3d", "mc";
306        };
307
308        dc@54200000 {
309            compatible = "nvidia,tegra20-dc";
310            reg = <0x54200000 0x00040000>;
311            interrupts = <0 73 0x04>;
312            clocks = <&tegra_car TEGRA20_CLK_DISP1>;
313            clock-names = "dc";
314            resets = <&tegra_car 27>;
315            reset-names = "dc";
316
317            rgb {
318            };
319        };
320
321        dc@54240000 {
322            compatible = "nvidia,tegra20-dc";
323            reg = <0x54240000 0x00040000>;
324            interrupts = <0 74 0x04>;
325            clocks = <&tegra_car TEGRA20_CLK_DISP2>;
326            clock-names = "dc";
327            resets = <&tegra_car 26>;
328            reset-names = "dc";
329
330            rgb {
331            };
332        };
333
334        hdmi@54280000 {
335            compatible = "nvidia,tegra20-hdmi";
336            reg = <0x54280000 0x00040000>;
337            interrupts = <0 75 0x04>;
338            clocks = <&tegra_car TEGRA20_CLK_HDMI>,
339                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
340            clock-names = "hdmi", "parent";
341            resets = <&tegra_car 51>;
342            reset-names = "hdmi";
343
344            hdmi-supply = <&vdd_5v0_hdmi>;
345            pll-supply = <&vdd_hdmi_pll>;
346            vdd-supply = <&vdd_3v3_hdmi>;
347
348            nvidia,ddc-i2c-bus = <&hdmi_ddc>;
349            nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
350        };
351
352        tvo@542c0000 {
353            compatible = "nvidia,tegra20-tvo";
354            reg = <0x542c0000 0x00040000>;
355            interrupts = <0 76 0x04>;
356            clocks = <&tegra_car TEGRA20_CLK_TVO>;
357        };
358
359        dsi@54300000 {
360            compatible = "nvidia,tegra20-dsi";
361            reg = <0x54300000 0x00040000>;
362            clocks = <&tegra_car TEGRA20_CLK_DSI>,
363                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
364            clock-names = "dsi", "parent";
365            resets = <&tegra_car 48>;
366            reset-names = "dsi";
367        };
368    };
369
370  - |
371    #include <dt-bindings/clock/tegra210-car.h>
372    #include <dt-bindings/interrupt-controller/arm-gic.h>
373    #include <dt-bindings/memory/tegra210-mc.h>
374
375    host1x@50000000 {
376        compatible = "nvidia,tegra210-host1x";
377        reg = <0x50000000 0x00024000>;
378        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
379                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
380        interrupt-names = "syncpt", "host1x";
381        clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
382        clock-names = "host1x";
383        resets = <&tegra_car 28>;
384        reset-names = "host1x";
385
386        #address-cells = <1>;
387        #size-cells = <1>;
388
389        ranges = <0x54000000 0x54000000 0x01000000>;
390        iommus = <&mc TEGRA_SWGROUP_HC>;
391
392        vi@54080000 {
393            compatible = "nvidia,tegra210-vi";
394            reg = <0x54080000 0x00000700>;
395            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
396            assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
397            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
398
399            clocks = <&tegra_car TEGRA210_CLK_VI>;
400            power-domains = <&pd_venc>;
401
402            #address-cells = <1>;
403            #size-cells = <1>;
404
405            ranges = <0x0 0x54080000 0x2000>;
406
407            csi@838 {
408                compatible = "nvidia,tegra210-csi";
409                reg = <0x838 0x1300>;
410                assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
411                                  <&tegra_car TEGRA210_CLK_CILCD>,
412                                  <&tegra_car TEGRA210_CLK_CILE>,
413                                  <&tegra_car TEGRA210_CLK_CSI_TPG>;
414                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
415                                         <&tegra_car TEGRA210_CLK_PLL_P>,
416                                         <&tegra_car TEGRA210_CLK_PLL_P>;
417                assigned-clock-rates = <102000000>,
418                                       <102000000>,
419                                       <102000000>,
420                                       <972000000>;
421
422                clocks = <&tegra_car TEGRA210_CLK_CSI>,
423                         <&tegra_car TEGRA210_CLK_CILAB>,
424                         <&tegra_car TEGRA210_CLK_CILCD>,
425                         <&tegra_car TEGRA210_CLK_CILE>,
426                         <&tegra_car TEGRA210_CLK_CSI_TPG>;
427                clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
428                power-domains = <&pd_sor>;
429            };
430        };
431    };
432