1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra host1x controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: The host1x top-level node defines a number of children, each 14 representing one of the host1x client modules defined in this binding. 15 16properties: 17 compatible: 18 oneOf: 19 - enum: 20 - nvidia,tegra20-host1x 21 - nvidia,tegra30-host1x 22 - nvidia,tegra114-host1x 23 - nvidia,tegra124-host1x 24 - nvidia,tegra210-host1x 25 - nvidia,tegra186-host1x 26 - nvidia,tegra194-host1x 27 - nvidia,tegra234-host1x 28 29 - items: 30 - const: nvidia,tegra132-host1x 31 - const: nvidia,tegra124-host1x 32 33 reg: 34 minItems: 1 35 maxItems: 3 36 37 reg-names: 38 minItems: 1 39 maxItems: 3 40 41 interrupts: 42 minItems: 1 43 maxItems: 9 44 45 interrupt-names: 46 minItems: 1 47 maxItems: 9 48 49 '#address-cells': 50 description: The number of cells used to represent physical base addresses 51 in the host1x address space. 52 enum: [1, 2] 53 54 '#size-cells': 55 description: The number of cells used to represent the size of an address 56 range in the host1x address space. 57 enum: [1, 2] 58 59 ranges: 60 maxItems: 1 61 62 clocks: 63 description: Must contain one entry, for the module clock. See 64 ../clocks/clock-bindings.txt for details. 65 66 clock-names: 67 items: 68 - const: host1x 69 70 resets: 71 minItems: 1 # MC reset is optional on Tegra186 and later 72 items: 73 - description: module reset 74 - description: memory client hotflush reset 75 76 reset-names: 77 minItems: 1 # MC reset is optional on Tegra186 and later 78 items: 79 - const: host1x 80 - const: mc 81 82 iommus: 83 maxItems: 1 84 85 interconnects: 86 items: 87 - description: memory read client for host1x 88 89 interconnect-names: 90 items: 91 - const: dma-mem # read 92 93 operating-points-v2: true 94 95 power-domains: 96 items: 97 - description: phandle to the HEG or core power domain 98 99required: 100 - compatible 101 - interrupts 102 - interrupt-names 103 - '#address-cells' 104 - '#size-cells' 105 - ranges 106 - reg 107 - clocks 108 - clock-names 109 110unevaluatedProperties: 111 type: object 112 113allOf: 114 - if: 115 properties: 116 compatible: 117 contains: 118 enum: 119 - nvidia,tegra20-host1x 120 - nvidia,tegra30-host1x 121 - nvidia,tegra114-host1x 122 - nvidia,tegra124-host1x 123 - nvidia,tegra210-host1x 124 then: 125 properties: 126 interrupts: 127 items: 128 - description: host1x syncpoint interrupt 129 - description: host1x general interrupt 130 131 interrupt-names: 132 items: 133 - const: syncpt 134 - const: host1x 135 required: 136 - resets 137 - reset-names 138 - if: 139 properties: 140 compatible: 141 contains: 142 enum: 143 - nvidia,tegra186-host1x 144 - nvidia,tegra194-host1x 145 then: 146 properties: 147 reg-names: 148 items: 149 - const: hypervisor 150 - const: vm 151 152 reg: 153 items: 154 - description: region used by the hypervisor 155 - description: region assigned to the virtual machine 156 157 resets: 158 maxItems: 1 159 160 reset-names: 161 maxItems: 1 162 163 interrupts: 164 items: 165 - description: host1x syncpoint interrupt 166 - description: host1x general interrupt 167 168 interrupt-names: 169 items: 170 - const: syncpt 171 - const: host1x 172 173 iommu-map: 174 description: Specification of stream IDs available for memory context device 175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to 176 usable stream IDs. 177 178 required: 179 - reg-names 180 - if: 181 properties: 182 compatible: 183 contains: 184 enum: 185 - nvidia,tegra234-host1x 186 then: 187 properties: 188 reg-names: 189 items: 190 - const: common 191 - const: hypervisor 192 - const: vm 193 194 reg: 195 items: 196 - description: region used by host1x server 197 - description: region used by the hypervisor 198 - description: region assigned to the virtual machine 199 200 interrupts: 201 items: 202 - description: host1x syncpoint interrupt 0 203 - description: host1x syncpoint interrupt 1 204 - description: host1x syncpoint interrupt 2 205 - description: host1x syncpoint interrupt 3 206 - description: host1x syncpoint interrupt 4 207 - description: host1x syncpoint interrupt 5 208 - description: host1x syncpoint interrupt 6 209 - description: host1x syncpoint interrupt 7 210 - description: host1x general interrupt 211 212 interrupt-names: 213 items: 214 - const: syncpt0 215 - const: syncpt1 216 - const: syncpt2 217 - const: syncpt3 218 - const: syncpt4 219 - const: syncpt5 220 - const: syncpt6 221 - const: syncpt7 222 - const: host1x 223 224 iommu-map: 225 description: Specification of stream IDs available for memory context device 226 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to 227 usable stream IDs. 228 229 required: 230 - reg-names 231 232examples: 233 - | 234 #include <dt-bindings/clock/tegra20-car.h> 235 #include <dt-bindings/gpio/tegra-gpio.h> 236 #include <dt-bindings/memory/tegra20-mc.h> 237 238 host1x@50000000 { 239 compatible = "nvidia,tegra20-host1x"; 240 reg = <0x50000000 0x00024000>; 241 interrupts = <0 65 0x04>, /* mpcore syncpt */ 242 <0 67 0x04>; /* mpcore general */ 243 interrupt-names = "syncpt", "host1x"; 244 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 245 clock-names = "host1x"; 246 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; 247 reset-names = "host1x", "mc"; 248 249 #address-cells = <1>; 250 #size-cells = <1>; 251 252 ranges = <0x54000000 0x54000000 0x04000000>; 253 254 mpe@54040000 { 255 compatible = "nvidia,tegra20-mpe"; 256 reg = <0x54040000 0x00040000>; 257 interrupts = <0 68 0x04>; 258 clocks = <&tegra_car TEGRA20_CLK_MPE>; 259 resets = <&tegra_car 60>; 260 reset-names = "mpe"; 261 }; 262 263 vi@54080000 { 264 compatible = "nvidia,tegra20-vi"; 265 reg = <0x54080000 0x00040000>; 266 interrupts = <0 69 0x04>; 267 clocks = <&tegra_car TEGRA20_CLK_VI>; 268 resets = <&tegra_car 100>; 269 reset-names = "vi"; 270 }; 271 272 epp@540c0000 { 273 compatible = "nvidia,tegra20-epp"; 274 reg = <0x540c0000 0x00040000>; 275 interrupts = <0 70 0x04>; 276 clocks = <&tegra_car TEGRA20_CLK_EPP>; 277 resets = <&tegra_car 19>; 278 reset-names = "epp"; 279 }; 280 281 isp@54100000 { 282 compatible = "nvidia,tegra20-isp"; 283 reg = <0x54100000 0x00040000>; 284 interrupts = <0 71 0x04>; 285 clocks = <&tegra_car TEGRA20_CLK_ISP>; 286 resets = <&tegra_car 23>; 287 reset-names = "isp"; 288 }; 289 290 gr2d@54140000 { 291 compatible = "nvidia,tegra20-gr2d"; 292 reg = <0x54140000 0x00040000>; 293 interrupts = <0 72 0x04>; 294 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 295 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; 296 reset-names = "2d", "mc"; 297 }; 298 299 gr3d@54180000 { 300 compatible = "nvidia,tegra20-gr3d"; 301 reg = <0x54180000 0x00040000>; 302 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 303 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; 304 reset-names = "3d", "mc"; 305 }; 306 307 dc@54200000 { 308 compatible = "nvidia,tegra20-dc"; 309 reg = <0x54200000 0x00040000>; 310 interrupts = <0 73 0x04>; 311 clocks = <&tegra_car TEGRA20_CLK_DISP1>; 312 clock-names = "dc"; 313 resets = <&tegra_car 27>; 314 reset-names = "dc"; 315 316 rgb { 317 }; 318 }; 319 320 dc@54240000 { 321 compatible = "nvidia,tegra20-dc"; 322 reg = <0x54240000 0x00040000>; 323 interrupts = <0 74 0x04>; 324 clocks = <&tegra_car TEGRA20_CLK_DISP2>; 325 clock-names = "dc"; 326 resets = <&tegra_car 26>; 327 reset-names = "dc"; 328 329 rgb { 330 }; 331 }; 332 333 hdmi@54280000 { 334 compatible = "nvidia,tegra20-hdmi"; 335 reg = <0x54280000 0x00040000>; 336 interrupts = <0 75 0x04>; 337 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 338 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 339 clock-names = "hdmi", "parent"; 340 resets = <&tegra_car 51>; 341 reset-names = "hdmi"; 342 343 hdmi-supply = <&vdd_5v0_hdmi>; 344 pll-supply = <&vdd_hdmi_pll>; 345 vdd-supply = <&vdd_3v3_hdmi>; 346 347 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 348 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 349 }; 350 351 tvo@542c0000 { 352 compatible = "nvidia,tegra20-tvo"; 353 reg = <0x542c0000 0x00040000>; 354 interrupts = <0 76 0x04>; 355 clocks = <&tegra_car TEGRA20_CLK_TVO>; 356 }; 357 358 dsi@54300000 { 359 compatible = "nvidia,tegra20-dsi"; 360 reg = <0x54300000 0x00040000>; 361 clocks = <&tegra_car TEGRA20_CLK_DSI>, 362 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 363 clock-names = "dsi", "parent"; 364 resets = <&tegra_car 48>; 365 reset-names = "dsi"; 366 }; 367 }; 368 369 - | 370 #include <dt-bindings/clock/tegra210-car.h> 371 #include <dt-bindings/interrupt-controller/arm-gic.h> 372 #include <dt-bindings/memory/tegra210-mc.h> 373 374 host1x@50000000 { 375 compatible = "nvidia,tegra210-host1x"; 376 reg = <0x50000000 0x00024000>; 377 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */ 378 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */ 379 interrupt-names = "syncpt", "host1x"; 380 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 381 clock-names = "host1x"; 382 resets = <&tegra_car 28>; 383 reset-names = "host1x"; 384 385 #address-cells = <1>; 386 #size-cells = <1>; 387 388 ranges = <0x54000000 0x54000000 0x01000000>; 389 iommus = <&mc TEGRA_SWGROUP_HC>; 390 391 vi@54080000 { 392 compatible = "nvidia,tegra210-vi"; 393 reg = <0x54080000 0x00000700>; 394 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 395 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 396 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 397 398 clocks = <&tegra_car TEGRA210_CLK_VI>; 399 power-domains = <&pd_venc>; 400 401 #address-cells = <1>; 402 #size-cells = <1>; 403 404 ranges = <0x0 0x54080000 0x2000>; 405 406 csi@838 { 407 compatible = "nvidia,tegra210-csi"; 408 reg = <0x838 0x1300>; 409 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 410 <&tegra_car TEGRA210_CLK_CILCD>, 411 <&tegra_car TEGRA210_CLK_CILE>, 412 <&tegra_car TEGRA210_CLK_CSI_TPG>; 413 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 414 <&tegra_car TEGRA210_CLK_PLL_P>, 415 <&tegra_car TEGRA210_CLK_PLL_P>; 416 assigned-clock-rates = <102000000>, 417 <102000000>, 418 <102000000>, 419 <972000000>; 420 421 clocks = <&tegra_car TEGRA210_CLK_CSI>, 422 <&tegra_car TEGRA210_CLK_CILAB>, 423 <&tegra_car TEGRA210_CLK_CILCD>, 424 <&tegra_car TEGRA210_CLK_CILE>, 425 <&tegra_car TEGRA210_CLK_CSI_TPG>; 426 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 427 power-domains = <&pd_sor>; 428 }; 429 }; 430 }; 431