1NVIDIA Tegra host1x 2 3Required properties: 4- compatible: "nvidia,tegra<chip>-host1x" 5- reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10- interrupts: The interrupt outputs from the controller. 11- #address-cells: The number of cells used to represent physical base addresses 12 in the host1x address space. Should be 1. 13- #size-cells: The number of cells used to represent the size of an address 14 range in the host1x address space. Should be 1. 15- ranges: The mapping of the host1x address space to the CPU address space. 16- clocks: Must contain one entry, for the module clock. 17 See ../clocks/clock-bindings.txt for details. 18- resets: Must contain an entry for each entry in reset-names. 19 See ../reset/reset.txt for details. 20- reset-names: Must include the following entries: 21 - host1x 22 23The host1x top-level node defines a number of children, each representing one 24of the following host1x client modules: 25 26- mpe: video encoder 27 28 Required properties: 29 - compatible: "nvidia,tegra<chip>-mpe" 30 - reg: Physical base address and length of the controller's registers. 31 - interrupts: The interrupt outputs from the controller. 32 - clocks: Must contain one entry, for the module clock. 33 See ../clocks/clock-bindings.txt for details. 34 - resets: Must contain an entry for each entry in reset-names. 35 See ../reset/reset.txt for details. 36 - reset-names: Must include the following entries: 37 - mpe 38 39- vi: video input 40 41 Required properties: 42 - compatible: "nvidia,tegra<chip>-vi" 43 - reg: Physical base address and length of the controller registers. 44 - interrupts: The interrupt outputs from the controller. 45 - clocks: clocks: Must contain one entry, for the module clock. 46 See ../clocks/clock-bindings.txt for details. 47 - Tegra20/Tegra30/Tegra114/Tegra124: 48 - resets: Must contain an entry for each entry in reset-names. 49 See ../reset/reset.txt for details. 50 - reset-names: Must include the following entries: 51 - vi 52 - Tegra210: 53 - power-domains: Must include venc powergate node as vi is in VE partition. 54 - Tegra210 has CSI part of VI sharing same host interface and register space. 55 So, VI device node should have CSI child node. 56 57 - csi: mipi csi interface to vi 58 59 Required properties: 60 - compatible: "nvidia,tegra210-csi" 61 - reg: Physical base address offset to parent and length of the controller 62 registers. 63 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. 64 See ../clocks/clock-bindings.txt for details. 65 - power-domains: Must include sor powergate node as csicil is in 66 SOR partition. 67 68- epp: encoder pre-processor 69 70 Required properties: 71 - compatible: "nvidia,tegra<chip>-epp" 72 - reg: Physical base address and length of the controller's registers. 73 - interrupts: The interrupt outputs from the controller. 74 - clocks: Must contain one entry, for the module clock. 75 See ../clocks/clock-bindings.txt for details. 76 - resets: Must contain an entry for each entry in reset-names. 77 See ../reset/reset.txt for details. 78 - reset-names: Must include the following entries: 79 - epp 80 81- isp: image signal processor 82 83 Required properties: 84 - compatible: "nvidia,tegra<chip>-isp" 85 - reg: Physical base address and length of the controller's registers. 86 - interrupts: The interrupt outputs from the controller. 87 - clocks: Must contain one entry, for the module clock. 88 See ../clocks/clock-bindings.txt for details. 89 - resets: Must contain an entry for each entry in reset-names. 90 See ../reset/reset.txt for details. 91 - reset-names: Must include the following entries: 92 - isp 93 94- gr2d: 2D graphics engine 95 96 Required properties: 97 - compatible: "nvidia,tegra<chip>-gr2d" 98 - reg: Physical base address and length of the controller's registers. 99 - interrupts: The interrupt outputs from the controller. 100 - clocks: Must contain one entry, for the module clock. 101 See ../clocks/clock-bindings.txt for details. 102 - resets: Must contain an entry for each entry in reset-names. 103 See ../reset/reset.txt for details. 104 - reset-names: Must include the following entries: 105 - 2d 106 107- gr3d: 3D graphics engine 108 109 Required properties: 110 - compatible: "nvidia,tegra<chip>-gr3d" 111 - reg: Physical base address and length of the controller's registers. 112 - clocks: Must contain an entry for each entry in clock-names. 113 See ../clocks/clock-bindings.txt for details. 114 - clock-names: Must include the following entries: 115 (This property may be omitted if the only clock in the list is "3d") 116 - 3d 117 This MUST be the first entry. 118 - 3d2 (Only required on SoCs with two 3D clocks) 119 - resets: Must contain an entry for each entry in reset-names. 120 See ../reset/reset.txt for details. 121 - reset-names: Must include the following entries: 122 - 3d 123 - 3d2 (Only required on SoCs with two 3D clocks) 124 125- dc: display controller 126 127 Required properties: 128 - compatible: "nvidia,tegra<chip>-dc" 129 - reg: Physical base address and length of the controller's registers. 130 - interrupts: The interrupt outputs from the controller. 131 - clocks: Must contain an entry for each entry in clock-names. 132 See ../clocks/clock-bindings.txt for details. 133 - clock-names: Must include the following entries: 134 - dc 135 This MUST be the first entry. 136 - parent 137 - resets: Must contain an entry for each entry in reset-names. 138 See ../reset/reset.txt for details. 139 - reset-names: Must include the following entries: 140 - dc 141 - nvidia,head: The number of the display controller head. This is used to 142 setup the various types of output to receive video data from the given 143 head. 144 145 Each display controller node has a child node, named "rgb", that represents 146 the RGB output associated with the controller. It can take the following 147 optional properties: 148 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 149 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 150 - nvidia,edid: supplies a binary EDID blob 151 - nvidia,panel: phandle of a display panel 152 153- hdmi: High Definition Multimedia Interface 154 155 Required properties: 156 - compatible: "nvidia,tegra<chip>-hdmi" 157 - reg: Physical base address and length of the controller's registers. 158 - interrupts: The interrupt outputs from the controller. 159 - hdmi-supply: supply for the +5V HDMI connector pin 160 - vdd-supply: regulator for supply voltage 161 - pll-supply: regulator for PLL 162 - clocks: Must contain an entry for each entry in clock-names. 163 See ../clocks/clock-bindings.txt for details. 164 - clock-names: Must include the following entries: 165 - hdmi 166 This MUST be the first entry. 167 - parent 168 - resets: Must contain an entry for each entry in reset-names. 169 See ../reset/reset.txt for details. 170 - reset-names: Must include the following entries: 171 - hdmi 172 173 Optional properties: 174 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 175 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 176 - nvidia,edid: supplies a binary EDID blob 177 - nvidia,panel: phandle of a display panel 178 179- tvo: TV encoder output 180 181 Required properties: 182 - compatible: "nvidia,tegra<chip>-tvo" 183 - reg: Physical base address and length of the controller's registers. 184 - interrupts: The interrupt outputs from the controller. 185 - clocks: Must contain one entry, for the module clock. 186 See ../clocks/clock-bindings.txt for details. 187 188- dsi: display serial interface 189 190 Required properties: 191 - compatible: "nvidia,tegra<chip>-dsi" 192 - reg: Physical base address and length of the controller's registers. 193 - clocks: Must contain an entry for each entry in clock-names. 194 See ../clocks/clock-bindings.txt for details. 195 - clock-names: Must include the following entries: 196 - dsi 197 This MUST be the first entry. 198 - lp 199 - parent 200 - resets: Must contain an entry for each entry in reset-names. 201 See ../reset/reset.txt for details. 202 - reset-names: Must include the following entries: 203 - dsi 204 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 205 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 206 which pads are used by this DSI output and need to be calibrated. See also 207 ../display/tegra/nvidia,tegra114-mipi.txt. 208 209 Optional properties: 210 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 211 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 212 - nvidia,edid: supplies a binary EDID blob 213 - nvidia,panel: phandle of a display panel 214 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 215 up with in order to support up to 8 data lanes 216 217- sor: serial output resource 218 219 Required properties: 220 - compatible: Should be: 221 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 222 - "nvidia,tegra132-sor": for Tegra132 223 - "nvidia,tegra210-sor": for Tegra210 224 - "nvidia,tegra210-sor1": for Tegra210 225 - "nvidia,tegra186-sor": for Tegra186 226 - "nvidia,tegra186-sor1": for Tegra186 227 - reg: Physical base address and length of the controller's registers. 228 - interrupts: The interrupt outputs from the controller. 229 - clocks: Must contain an entry for each entry in clock-names. 230 See ../clocks/clock-bindings.txt for details. 231 - clock-names: Must include the following entries: 232 - sor: clock input for the SOR hardware 233 - out: SOR output clock 234 - parent: input for the pixel clock 235 - dp: reference clock for the SOR clock 236 - safe: safe reference for the SOR clock during power up 237 238 For Tegra186 and later: 239 - pad: SOR pad output clock (on Tegra186 and later) 240 241 Obsolete: 242 - source: source clock for the SOR clock (obsolete, use "out" instead) 243 244 - resets: Must contain an entry for each entry in reset-names. 245 See ../reset/reset.txt for details. 246 - reset-names: Must include the following entries: 247 - sor 248 249 Required properties on Tegra186 and later: 250 - nvidia,interface: index of the SOR interface 251 252 Optional properties: 253 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 254 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 255 - nvidia,edid: supplies a binary EDID blob 256 - nvidia,panel: phandle of a display panel 257 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane 258 of the SOR, identified by the cell's index, is mapped via the crossbar to 259 the pad specified by the cell's value. 260 261 Optional properties when driving an eDP output: 262 - nvidia,dpaux: phandle to a DispayPort AUX interface 263 264- dpaux: DisplayPort AUX interface 265 - compatible : Should contain one of the following: 266 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 267 - "nvidia,tegra210-dpaux": for Tegra210 268 - reg: Physical base address and length of the controller's registers. 269 - interrupts: The interrupt outputs from the controller. 270 - clocks: Must contain an entry for each entry in clock-names. 271 See ../clocks/clock-bindings.txt for details. 272 - clock-names: Must include the following entries: 273 - dpaux: clock input for the DPAUX hardware 274 - parent: reference clock 275 - resets: Must contain an entry for each entry in reset-names. 276 See ../reset/reset.txt for details. 277 - reset-names: Must include the following entries: 278 - dpaux 279 - vdd-supply: phandle of a supply that powers the DisplayPort link 280 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 281 must be always present. If there are no I2C slave devices, an empty 282 node should be added. See ../../i2c/i2c.txt for more information. 283 284 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 285 regarding the DPAUX pad controller bindings. 286 287- vic: Video Image Compositor 288 - compatible : "nvidia,tegra<chip>-vic" 289 - reg: Physical base address and length of the controller's registers. 290 - interrupts: The interrupt outputs from the controller. 291 - clocks: Must contain an entry for each entry in clock-names. 292 See ../clocks/clock-bindings.txt for details. 293 - clock-names: Must include the following entries: 294 - vic: clock input for the VIC hardware 295 - resets: Must contain an entry for each entry in reset-names. 296 See ../reset/reset.txt for details. 297 - reset-names: Must include the following entries: 298 - vic 299 300Example: 301 302/ { 303 ... 304 305 host1x { 306 compatible = "nvidia,tegra20-host1x", "simple-bus"; 307 reg = <0x50000000 0x00024000>; 308 interrupts = <0 65 0x04 /* mpcore syncpt */ 309 0 67 0x04>; /* mpcore general */ 310 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 311 resets = <&tegra_car 28>; 312 reset-names = "host1x"; 313 314 #address-cells = <1>; 315 #size-cells = <1>; 316 317 ranges = <0x54000000 0x54000000 0x04000000>; 318 319 mpe { 320 compatible = "nvidia,tegra20-mpe"; 321 reg = <0x54040000 0x00040000>; 322 interrupts = <0 68 0x04>; 323 clocks = <&tegra_car TEGRA20_CLK_MPE>; 324 resets = <&tegra_car 60>; 325 reset-names = "mpe"; 326 }; 327 328 vi@54080000 { 329 compatible = "nvidia,tegra210-vi"; 330 reg = <0x0 0x54080000 0x0 0x700>; 331 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 332 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 333 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 334 335 clocks = <&tegra_car TEGRA210_CLK_VI>; 336 power-domains = <&pd_venc>; 337 338 #address-cells = <1>; 339 #size-cells = <1>; 340 341 ranges = <0x0 0x0 0x54080000 0x2000>; 342 343 csi@838 { 344 compatible = "nvidia,tegra210-csi"; 345 reg = <0x838 0x1300>; 346 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 347 <&tegra_car TEGRA210_CLK_CILCD>, 348 <&tegra_car TEGRA210_CLK_CILE>, 349 <&tegra_car TEGRA210_CLK_CSI_TPG>; 350 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 351 <&tegra_car TEGRA210_CLK_PLL_P>, 352 <&tegra_car TEGRA210_CLK_PLL_P>; 353 assigned-clock-rates = <102000000>, 354 <102000000>, 355 <102000000>, 356 <972000000>; 357 358 clocks = <&tegra_car TEGRA210_CLK_CSI>, 359 <&tegra_car TEGRA210_CLK_CILAB>, 360 <&tegra_car TEGRA210_CLK_CILCD>, 361 <&tegra_car TEGRA210_CLK_CILE>, 362 <&tegra_car TEGRA210_CLK_CSI_TPG>; 363 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 364 power-domains = <&pd_sor>; 365 }; 366 }; 367 368 epp { 369 compatible = "nvidia,tegra20-epp"; 370 reg = <0x540c0000 0x00040000>; 371 interrupts = <0 70 0x04>; 372 clocks = <&tegra_car TEGRA20_CLK_EPP>; 373 resets = <&tegra_car 19>; 374 reset-names = "epp"; 375 }; 376 377 isp { 378 compatible = "nvidia,tegra20-isp"; 379 reg = <0x54100000 0x00040000>; 380 interrupts = <0 71 0x04>; 381 clocks = <&tegra_car TEGRA20_CLK_ISP>; 382 resets = <&tegra_car 23>; 383 reset-names = "isp"; 384 }; 385 386 gr2d { 387 compatible = "nvidia,tegra20-gr2d"; 388 reg = <0x54140000 0x00040000>; 389 interrupts = <0 72 0x04>; 390 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 391 resets = <&tegra_car 21>; 392 reset-names = "2d"; 393 }; 394 395 gr3d { 396 compatible = "nvidia,tegra20-gr3d"; 397 reg = <0x54180000 0x00040000>; 398 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 399 resets = <&tegra_car 24>; 400 reset-names = "3d"; 401 }; 402 403 dc@54200000 { 404 compatible = "nvidia,tegra20-dc"; 405 reg = <0x54200000 0x00040000>; 406 interrupts = <0 73 0x04>; 407 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 408 <&tegra_car TEGRA20_CLK_PLL_P>; 409 clock-names = "dc", "parent"; 410 resets = <&tegra_car 27>; 411 reset-names = "dc"; 412 413 rgb { 414 status = "disabled"; 415 }; 416 }; 417 418 dc@54240000 { 419 compatible = "nvidia,tegra20-dc"; 420 reg = <0x54240000 0x00040000>; 421 interrupts = <0 74 0x04>; 422 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 423 <&tegra_car TEGRA20_CLK_PLL_P>; 424 clock-names = "dc", "parent"; 425 resets = <&tegra_car 26>; 426 reset-names = "dc"; 427 428 rgb { 429 status = "disabled"; 430 }; 431 }; 432 433 hdmi { 434 compatible = "nvidia,tegra20-hdmi"; 435 reg = <0x54280000 0x00040000>; 436 interrupts = <0 75 0x04>; 437 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 438 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 439 clock-names = "hdmi", "parent"; 440 resets = <&tegra_car 51>; 441 reset-names = "hdmi"; 442 status = "disabled"; 443 }; 444 445 tvo { 446 compatible = "nvidia,tegra20-tvo"; 447 reg = <0x542c0000 0x00040000>; 448 interrupts = <0 76 0x04>; 449 clocks = <&tegra_car TEGRA20_CLK_TVO>; 450 status = "disabled"; 451 }; 452 453 dsi { 454 compatible = "nvidia,tegra20-dsi"; 455 reg = <0x54300000 0x00040000>; 456 clocks = <&tegra_car TEGRA20_CLK_DSI>, 457 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 458 clock-names = "dsi", "parent"; 459 resets = <&tegra_car 48>; 460 reset-names = "dsi"; 461 status = "disabled"; 462 }; 463 }; 464 465 ... 466}; 467