1NVIDIA Tegra host1x 2 3Required properties: 4- compatible: "nvidia,tegra<chip>-host1x" 5- reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10- interrupts: The interrupt outputs from the controller. 11- #address-cells: The number of cells used to represent physical base addresses 12 in the host1x address space. Should be 1. 13- #size-cells: The number of cells used to represent the size of an address 14 range in the host1x address space. Should be 1. 15- ranges: The mapping of the host1x address space to the CPU address space. 16- clocks: Must contain one entry, for the module clock. 17 See ../clocks/clock-bindings.txt for details. 18- resets: Must contain an entry for each entry in reset-names. 19 See ../reset/reset.txt for details. 20- reset-names: Must include the following entries: 21 - host1x 22 23Each host1x client module having to perform DMA through the Memory Controller 24should have the interconnect endpoints set to the Memory Client and External 25Memory respectively. 26 27The host1x top-level node defines a number of children, each representing one 28of the following host1x client modules: 29 30- mpe: video encoder 31 32 Required properties: 33 - compatible: "nvidia,tegra<chip>-mpe" 34 - reg: Physical base address and length of the controller's registers. 35 - interrupts: The interrupt outputs from the controller. 36 - clocks: Must contain one entry, for the module clock. 37 See ../clocks/clock-bindings.txt for details. 38 - resets: Must contain an entry for each entry in reset-names. 39 See ../reset/reset.txt for details. 40 - reset-names: Must include the following entries: 41 - mpe 42 43 Optional properties: 44 - interconnects: Must contain entry for the MPE memory clients. 45 - interconnect-names: Must include name of the interconnect path for each 46 interconnect entry. Consult TRM documentation for information about 47 available memory clients, see MEMORY CONTROLLER section. 48 49- vi: video input 50 51 Required properties: 52 - compatible: "nvidia,tegra<chip>-vi" 53 - reg: Physical base address and length of the controller registers. 54 - interrupts: The interrupt outputs from the controller. 55 - clocks: clocks: Must contain one entry, for the module clock. 56 See ../clocks/clock-bindings.txt for details. 57 - Tegra20/Tegra30/Tegra114/Tegra124: 58 - resets: Must contain an entry for each entry in reset-names. 59 See ../reset/reset.txt for details. 60 - reset-names: Must include the following entries: 61 - vi 62 - Tegra210: 63 - power-domains: Must include venc powergate node as vi is in VE partition. 64 65 ports (optional node) 66 vi can have optional ports node and max 6 ports are supported. Each port 67 should have single 'endpoint' child node. All port nodes are grouped under 68 ports node. Please refer to the bindings defined in 69 Documentation/devicetree/bindings/media/video-interfaces.txt 70 71 csi (required node) 72 Tegra210 has CSI part of VI sharing same host interface and register space. 73 So, VI device node should have CSI child node. 74 75 - csi: mipi csi interface to vi 76 77 Required properties: 78 - compatible: "nvidia,tegra210-csi" 79 - reg: Physical base address offset to parent and length of the controller 80 registers. 81 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. 82 See ../clocks/clock-bindings.txt for details. 83 - power-domains: Must include sor powergate node as csicil is in 84 SOR partition. 85 86 channel (optional nodes) 87 Maximum 6 channels are supported with each csi brick as either x4 or x2 88 based on hw connectivity to sensor. 89 90 Required properties: 91 - reg: csi port number. Valid port numbers are 0 through 5. 92 - nvidia,mipi-calibrate: Should contain a phandle and a specifier 93 specifying which pads are used by this CSI port and need to be 94 calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. 95 96 Each channel node must contain 2 port nodes which can be grouped 97 under 'ports' node and each port should have a single child 'endpoint' 98 node. 99 100 ports node 101 Please refer to the bindings defined in 102 Documentation/devicetree/bindings/media/video-interfaces.txt 103 104 ports node must contain below 2 port nodes. 105 port@0 with single child 'endpoint' node always a sink. 106 port@1 with single child 'endpoint' node always a source. 107 108 port@0 (required node) 109 Required properties: 110 - reg: 0 111 112 endpoint (required node) 113 Required properties: 114 - data-lanes: an array of data lane from 1 to 8. Valid array 115 lengths are 1/2/4/8. 116 - remote-endpoint: phandle to sensor 'endpoint' node. 117 118 port@1 (required node) 119 Required properties: 120 - reg: 1 121 122 endpoint (required node) 123 Required properties: 124 - remote-endpoint: phandle to vi port 'endpoint' node. 125 126 Optional properties: 127 - interconnects: Must contain entry for the VI memory clients. 128 - interconnect-names: Must include name of the interconnect path for each 129 interconnect entry. Consult TRM documentation for information about 130 available memory clients, see MEMORY CONTROLLER section. 131 132- epp: encoder pre-processor 133 134 Required properties: 135 - compatible: "nvidia,tegra<chip>-epp" 136 - reg: Physical base address and length of the controller's registers. 137 - interrupts: The interrupt outputs from the controller. 138 - clocks: Must contain one entry, for the module clock. 139 See ../clocks/clock-bindings.txt for details. 140 - resets: Must contain an entry for each entry in reset-names. 141 See ../reset/reset.txt for details. 142 - reset-names: Must include the following entries: 143 - epp 144 145 Optional properties: 146 - interconnects: Must contain entry for the EPP memory clients. 147 - interconnect-names: Must include name of the interconnect path for each 148 interconnect entry. Consult TRM documentation for information about 149 available memory clients, see MEMORY CONTROLLER section. 150 151- isp: image signal processor 152 153 Required properties: 154 - compatible: "nvidia,tegra<chip>-isp" 155 - reg: Physical base address and length of the controller's registers. 156 - interrupts: The interrupt outputs from the controller. 157 - clocks: Must contain one entry, for the module clock. 158 See ../clocks/clock-bindings.txt for details. 159 - resets: Must contain an entry for each entry in reset-names. 160 See ../reset/reset.txt for details. 161 - reset-names: Must include the following entries: 162 - isp 163 164 Optional properties: 165 - interconnects: Must contain entry for the ISP memory clients. 166 - interconnect-names: Must include name of the interconnect path for each 167 interconnect entry. Consult TRM documentation for information about 168 available memory clients, see MEMORY CONTROLLER section. 169 170- gr2d: 2D graphics engine 171 172 Required properties: 173 - compatible: "nvidia,tegra<chip>-gr2d" 174 - reg: Physical base address and length of the controller's registers. 175 - interrupts: The interrupt outputs from the controller. 176 - clocks: Must contain one entry, for the module clock. 177 See ../clocks/clock-bindings.txt for details. 178 - resets: Must contain an entry for each entry in reset-names. 179 See ../reset/reset.txt for details. 180 - reset-names: Must include the following entries: 181 - 2d 182 183 Optional properties: 184 - interconnects: Must contain entry for the GR2D memory clients. 185 - interconnect-names: Must include name of the interconnect path for each 186 interconnect entry. Consult TRM documentation for information about 187 available memory clients, see MEMORY CONTROLLER section. 188 189- gr3d: 3D graphics engine 190 191 Required properties: 192 - compatible: "nvidia,tegra<chip>-gr3d" 193 - reg: Physical base address and length of the controller's registers. 194 - clocks: Must contain an entry for each entry in clock-names. 195 See ../clocks/clock-bindings.txt for details. 196 - clock-names: Must include the following entries: 197 (This property may be omitted if the only clock in the list is "3d") 198 - 3d 199 This MUST be the first entry. 200 - 3d2 (Only required on SoCs with two 3D clocks) 201 - resets: Must contain an entry for each entry in reset-names. 202 See ../reset/reset.txt for details. 203 - reset-names: Must include the following entries: 204 - 3d 205 - 3d2 (Only required on SoCs with two 3D clocks) 206 207 Optional properties: 208 - interconnects: Must contain entry for the GR3D memory clients. 209 - interconnect-names: Must include name of the interconnect path for each 210 interconnect entry. Consult TRM documentation for information about 211 available memory clients, see MEMORY CONTROLLER section. 212 213- dc: display controller 214 215 Required properties: 216 - compatible: "nvidia,tegra<chip>-dc" 217 - reg: Physical base address and length of the controller's registers. 218 - interrupts: The interrupt outputs from the controller. 219 - clocks: Must contain an entry for each entry in clock-names. 220 See ../clocks/clock-bindings.txt for details. 221 - clock-names: Must include the following entries: 222 - dc 223 This MUST be the first entry. 224 - parent 225 - resets: Must contain an entry for each entry in reset-names. 226 See ../reset/reset.txt for details. 227 - reset-names: Must include the following entries: 228 - dc 229 - nvidia,head: The number of the display controller head. This is used to 230 setup the various types of output to receive video data from the given 231 head. 232 233 Each display controller node has a child node, named "rgb", that represents 234 the RGB output associated with the controller. It can take the following 235 optional properties: 236 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 237 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 238 - nvidia,edid: supplies a binary EDID blob 239 - nvidia,panel: phandle of a display panel 240 - interconnects: Must contain entry for the DC memory clients. 241 - interconnect-names: Must include name of the interconnect path for each 242 interconnect entry. Consult TRM documentation for information about 243 available memory clients, see MEMORY CONTROLLER section. 244 245- hdmi: High Definition Multimedia Interface 246 247 Required properties: 248 - compatible: "nvidia,tegra<chip>-hdmi" 249 - reg: Physical base address and length of the controller's registers. 250 - interrupts: The interrupt outputs from the controller. 251 - hdmi-supply: supply for the +5V HDMI connector pin 252 - vdd-supply: regulator for supply voltage 253 - pll-supply: regulator for PLL 254 - clocks: Must contain an entry for each entry in clock-names. 255 See ../clocks/clock-bindings.txt for details. 256 - clock-names: Must include the following entries: 257 - hdmi 258 This MUST be the first entry. 259 - parent 260 - resets: Must contain an entry for each entry in reset-names. 261 See ../reset/reset.txt for details. 262 - reset-names: Must include the following entries: 263 - hdmi 264 265 Optional properties: 266 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 267 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 268 - nvidia,edid: supplies a binary EDID blob 269 - nvidia,panel: phandle of a display panel 270 271- tvo: TV encoder output 272 273 Required properties: 274 - compatible: "nvidia,tegra<chip>-tvo" 275 - reg: Physical base address and length of the controller's registers. 276 - interrupts: The interrupt outputs from the controller. 277 - clocks: Must contain one entry, for the module clock. 278 See ../clocks/clock-bindings.txt for details. 279 280- dsi: display serial interface 281 282 Required properties: 283 - compatible: "nvidia,tegra<chip>-dsi" 284 - reg: Physical base address and length of the controller's registers. 285 - clocks: Must contain an entry for each entry in clock-names. 286 See ../clocks/clock-bindings.txt for details. 287 - clock-names: Must include the following entries: 288 - dsi 289 This MUST be the first entry. 290 - lp 291 - parent 292 - resets: Must contain an entry for each entry in reset-names. 293 See ../reset/reset.txt for details. 294 - reset-names: Must include the following entries: 295 - dsi 296 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 297 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 298 which pads are used by this DSI output and need to be calibrated. See also 299 ../display/tegra/nvidia,tegra114-mipi.txt. 300 301 Optional properties: 302 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 303 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 304 - nvidia,edid: supplies a binary EDID blob 305 - nvidia,panel: phandle of a display panel 306 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 307 up with in order to support up to 8 data lanes 308 309- sor: serial output resource 310 311 Required properties: 312 - compatible: Should be: 313 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 314 - "nvidia,tegra132-sor": for Tegra132 315 - "nvidia,tegra210-sor": for Tegra210 316 - "nvidia,tegra210-sor1": for Tegra210 317 - "nvidia,tegra186-sor": for Tegra186 318 - "nvidia,tegra186-sor1": for Tegra186 319 - reg: Physical base address and length of the controller's registers. 320 - interrupts: The interrupt outputs from the controller. 321 - clocks: Must contain an entry for each entry in clock-names. 322 See ../clocks/clock-bindings.txt for details. 323 - clock-names: Must include the following entries: 324 - sor: clock input for the SOR hardware 325 - out: SOR output clock 326 - parent: input for the pixel clock 327 - dp: reference clock for the SOR clock 328 - safe: safe reference for the SOR clock during power up 329 330 For Tegra186 and later: 331 - pad: SOR pad output clock (on Tegra186 and later) 332 333 Obsolete: 334 - source: source clock for the SOR clock (obsolete, use "out" instead) 335 336 - resets: Must contain an entry for each entry in reset-names. 337 See ../reset/reset.txt for details. 338 - reset-names: Must include the following entries: 339 - sor 340 341 Required properties on Tegra186 and later: 342 - nvidia,interface: index of the SOR interface 343 344 Optional properties: 345 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 346 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 347 - nvidia,edid: supplies a binary EDID blob 348 - nvidia,panel: phandle of a display panel 349 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane 350 of the SOR, identified by the cell's index, is mapped via the crossbar to 351 the pad specified by the cell's value. 352 353 Optional properties when driving an eDP output: 354 - nvidia,dpaux: phandle to a DispayPort AUX interface 355 356- dpaux: DisplayPort AUX interface 357 - compatible : Should contain one of the following: 358 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 359 - "nvidia,tegra210-dpaux": for Tegra210 360 - reg: Physical base address and length of the controller's registers. 361 - interrupts: The interrupt outputs from the controller. 362 - clocks: Must contain an entry for each entry in clock-names. 363 See ../clocks/clock-bindings.txt for details. 364 - clock-names: Must include the following entries: 365 - dpaux: clock input for the DPAUX hardware 366 - parent: reference clock 367 - resets: Must contain an entry for each entry in reset-names. 368 See ../reset/reset.txt for details. 369 - reset-names: Must include the following entries: 370 - dpaux 371 - vdd-supply: phandle of a supply that powers the DisplayPort link 372 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 373 must be always present. If there are no I2C slave devices, an empty 374 node should be added. See ../../i2c/i2c.txt for more information. 375 376 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 377 regarding the DPAUX pad controller bindings. 378 379- vic: Video Image Compositor 380 - compatible : "nvidia,tegra<chip>-vic" 381 - reg: Physical base address and length of the controller's registers. 382 - interrupts: The interrupt outputs from the controller. 383 - clocks: Must contain an entry for each entry in clock-names. 384 See ../clocks/clock-bindings.txt for details. 385 - clock-names: Must include the following entries: 386 - vic: clock input for the VIC hardware 387 - resets: Must contain an entry for each entry in reset-names. 388 See ../reset/reset.txt for details. 389 - reset-names: Must include the following entries: 390 - vic 391 392 Optional properties: 393 - interconnects: Must contain entry for the VIC memory clients. 394 - interconnect-names: Must include name of the interconnect path for each 395 interconnect entry. Consult TRM documentation for information about 396 available memory clients, see MEMORY CONTROLLER section. 397 398Example: 399 400/ { 401 ... 402 403 host1x { 404 compatible = "nvidia,tegra20-host1x", "simple-bus"; 405 reg = <0x50000000 0x00024000>; 406 interrupts = <0 65 0x04 /* mpcore syncpt */ 407 0 67 0x04>; /* mpcore general */ 408 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 409 resets = <&tegra_car 28>; 410 reset-names = "host1x"; 411 412 #address-cells = <1>; 413 #size-cells = <1>; 414 415 ranges = <0x54000000 0x54000000 0x04000000>; 416 417 mpe { 418 compatible = "nvidia,tegra20-mpe"; 419 reg = <0x54040000 0x00040000>; 420 interrupts = <0 68 0x04>; 421 clocks = <&tegra_car TEGRA20_CLK_MPE>; 422 resets = <&tegra_car 60>; 423 reset-names = "mpe"; 424 }; 425 426 vi@54080000 { 427 compatible = "nvidia,tegra210-vi"; 428 reg = <0x0 0x54080000 0x0 0x700>; 429 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 430 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 431 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 432 433 clocks = <&tegra_car TEGRA210_CLK_VI>; 434 power-domains = <&pd_venc>; 435 436 #address-cells = <1>; 437 #size-cells = <1>; 438 439 ranges = <0x0 0x0 0x54080000 0x2000>; 440 441 ports { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 445 port@0 { 446 reg = <0>; 447 imx219_vi_in0: endpoint { 448 remote-endpoint = <&imx219_csi_out0>; 449 }; 450 }; 451 }; 452 453 csi@838 { 454 compatible = "nvidia,tegra210-csi"; 455 reg = <0x838 0x1300>; 456 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 457 <&tegra_car TEGRA210_CLK_CILCD>, 458 <&tegra_car TEGRA210_CLK_CILE>, 459 <&tegra_car TEGRA210_CLK_CSI_TPG>; 460 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 461 <&tegra_car TEGRA210_CLK_PLL_P>, 462 <&tegra_car TEGRA210_CLK_PLL_P>; 463 assigned-clock-rates = <102000000>, 464 <102000000>, 465 <102000000>, 466 <972000000>; 467 468 clocks = <&tegra_car TEGRA210_CLK_CSI>, 469 <&tegra_car TEGRA210_CLK_CILAB>, 470 <&tegra_car TEGRA210_CLK_CILCD>, 471 <&tegra_car TEGRA210_CLK_CILE>, 472 <&tegra_car TEGRA210_CLK_CSI_TPG>; 473 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 474 power-domains = <&pd_sor>; 475 476 #address-cells = <1>; 477 #size-cells = <0>; 478 479 channel@0 { 480 reg = <0>; 481 nvidia,mipi-calibrate = <&mipi 0x001>; 482 483 ports { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 487 port@0 { 488 reg = <0>; 489 imx219_csi_in0: endpoint { 490 data-lanes = <1 2>; 491 remote-endpoint = <&imx219_out0>; 492 }; 493 }; 494 495 port@1 { 496 reg = <1>; 497 imx219_csi_out0: endpoint { 498 remote-endpoint = <&imx219_vi_in0>; 499 }; 500 }; 501 }; 502 }; 503 }; 504 }; 505 506 epp { 507 compatible = "nvidia,tegra20-epp"; 508 reg = <0x540c0000 0x00040000>; 509 interrupts = <0 70 0x04>; 510 clocks = <&tegra_car TEGRA20_CLK_EPP>; 511 resets = <&tegra_car 19>; 512 reset-names = "epp"; 513 }; 514 515 isp { 516 compatible = "nvidia,tegra20-isp"; 517 reg = <0x54100000 0x00040000>; 518 interrupts = <0 71 0x04>; 519 clocks = <&tegra_car TEGRA20_CLK_ISP>; 520 resets = <&tegra_car 23>; 521 reset-names = "isp"; 522 }; 523 524 gr2d { 525 compatible = "nvidia,tegra20-gr2d"; 526 reg = <0x54140000 0x00040000>; 527 interrupts = <0 72 0x04>; 528 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 529 resets = <&tegra_car 21>; 530 reset-names = "2d"; 531 }; 532 533 gr3d { 534 compatible = "nvidia,tegra20-gr3d"; 535 reg = <0x54180000 0x00040000>; 536 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 537 resets = <&tegra_car 24>; 538 reset-names = "3d"; 539 }; 540 541 dc@54200000 { 542 compatible = "nvidia,tegra20-dc"; 543 reg = <0x54200000 0x00040000>; 544 interrupts = <0 73 0x04>; 545 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 546 <&tegra_car TEGRA20_CLK_PLL_P>; 547 clock-names = "dc", "parent"; 548 resets = <&tegra_car 27>; 549 reset-names = "dc"; 550 551 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, 552 <&mc TEGRA20_MC_DISPLAY0B &emc>, 553 <&mc TEGRA20_MC_DISPLAY0C &emc>, 554 <&mc TEGRA20_MC_DISPLAYHC &emc>; 555 interconnect-names = "wina", 556 "winb", 557 "winc", 558 "cursor"; 559 560 rgb { 561 status = "disabled"; 562 }; 563 }; 564 565 dc@54240000 { 566 compatible = "nvidia,tegra20-dc"; 567 reg = <0x54240000 0x00040000>; 568 interrupts = <0 74 0x04>; 569 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 570 <&tegra_car TEGRA20_CLK_PLL_P>; 571 clock-names = "dc", "parent"; 572 resets = <&tegra_car 26>; 573 reset-names = "dc"; 574 575 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, 576 <&mc TEGRA20_MC_DISPLAY0BB &emc>, 577 <&mc TEGRA20_MC_DISPLAY0CB &emc>, 578 <&mc TEGRA20_MC_DISPLAYHCB &emc>; 579 interconnect-names = "wina", 580 "winb", 581 "winc", 582 "cursor"; 583 584 rgb { 585 status = "disabled"; 586 }; 587 }; 588 589 hdmi { 590 compatible = "nvidia,tegra20-hdmi"; 591 reg = <0x54280000 0x00040000>; 592 interrupts = <0 75 0x04>; 593 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 594 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 595 clock-names = "hdmi", "parent"; 596 resets = <&tegra_car 51>; 597 reset-names = "hdmi"; 598 status = "disabled"; 599 }; 600 601 tvo { 602 compatible = "nvidia,tegra20-tvo"; 603 reg = <0x542c0000 0x00040000>; 604 interrupts = <0 76 0x04>; 605 clocks = <&tegra_car TEGRA20_CLK_TVO>; 606 status = "disabled"; 607 }; 608 609 dsi { 610 compatible = "nvidia,tegra20-dsi"; 611 reg = <0x54300000 0x00040000>; 612 clocks = <&tegra_car TEGRA20_CLK_DSI>, 613 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 614 clock-names = "dsi", "parent"; 615 resets = <&tegra_car 48>; 616 reset-names = "dsi"; 617 status = "disabled"; 618 }; 619 }; 620 621 ... 622}; 623