1ST-Ericsson Multi Channel Display Engine MCDE 2 3The ST-Ericsson MCDE is a display controller with support for compositing 4and displaying several channels memory resident graphics data on DSI or 5LCD displays or bridges. It is used in the ST-Ericsson U8500 platform. 6 7Required properties: 8 9- compatible: must be: 10 "ste,mcde" 11- reg: register base for the main MCDE control registers, should be 12 0x1000 in size 13- interrupts: the interrupt line for the MCDE 14- epod-supply: a phandle to the EPOD regulator 15- vana-supply: a phandle to the analog voltage regulator 16- clocks: an array of the MCDE clocks in this strict order: 17 MCDECLK (main MCDE clock), LCDCLK (LCD clock), PLLDSI 18 (HDMI clock), DSI0ESCLK (DSI0 energy save clock), 19 DSI1ESCLK (DSI1 energy save clock), DSI2ESCLK (DSI2 energy 20 save clock) 21- clock-names: must be the following array: 22 "mcde", "lcd", "hdmi" 23 to match the required clock inputs above. 24- #address-cells: should be <1> (for the DSI hosts that will be children) 25- #size-cells: should be <1> (for the DSI hosts that will be children) 26- ranges: this should always be stated 27 28Required subnodes: 29 30The devicetree must specify subnodes for the DSI host adapters. 31These must have the following characteristics: 32 33- compatible: must be: 34 "ste,mcde-dsi" 35- reg: must specify the register range for the DSI host 36- vana-supply: phandle to the VANA voltage regulator 37- clocks: phandles to the high speed and low power (energy save) clocks 38 the high speed clock is not present on the third (dsi2) block, so it 39 should only have the "lp" clock 40- clock-names: "hs" for the high speed clock and "lp" for the low power 41 (energy save) clock 42- #address-cells: should be <1> 43- #size-cells: should be <0> 44 45Display panels and bridges will appear as children on the DSI hosts, and 46the displays are connected to the DSI hosts using the common binding 47for video transmitter interfaces; see 48Documentation/devicetree/bindings/media/video-interfaces.txt 49 50If a DSI host is unused (not connected) it will have no children defined. 51 52Example: 53 54mcde@a0350000 { 55 compatible = "ste,mcde"; 56 reg = <0xa0350000 0x1000>; 57 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 58 epod-supply = <&db8500_b2r2_mcde_reg>; 59 vana-supply = <&ab8500_ldo_ana_reg>; 60 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ 61 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ 62 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ 63 clock-names = "mcde", "lcd", "hdmi"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges; 67 68 dsi0: dsi@a0351000 { 69 compatible = "ste,mcde-dsi"; 70 reg = <0xa0351000 0x1000>; 71 vana-supply = <&ab8500_ldo_ana_reg>; 72 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; 73 clock-names = "hs", "lp"; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 panel { 78 compatible = "samsung,s6d16d0"; 79 reg = <0>; 80 vdd1-supply = <&ab8500_ldo_aux1_reg>; 81 reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 82 }; 83 84 }; 85 dsi1: dsi@a0352000 { 86 compatible = "ste,mcde-dsi"; 87 reg = <0xa0352000 0x1000>; 88 vana-supply = <&ab8500_ldo_ana_reg>; 89 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; 90 clock-names = "hs", "lp"; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 }; 94 dsi2: dsi@a0353000 { 95 compatible = "ste,mcde-dsi"; 96 reg = <0xa0353000 0x1000>; 97 vana-supply = <&ab8500_ldo_ana_reg>; 98 /* This DSI port only has the Low Power / Energy Save clock */ 99 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; 100 clock-names = "lp"; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 }; 104}; 105