xref: /freebsd/sys/contrib/device-tree/Bindings/display/samsung/samsung,exynos7-decon.yaml (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
8
9maintainers:
10  - Inki Dae <inki.dae@samsung.com>
11  - Seung-Woo Kim <sw0312.kim@samsung.com>
12  - Kyungmin Park <kyungmin.park@samsung.com>
13  - Krzysztof Kozlowski <krzk@kernel.org>
14
15description: |
16  DECON (Display and Enhancement Controller) is the Display Controller for the
17  Exynos7 series of SoCs which transfers the image data from a video memory
18  buffer to an external LCD interface.
19
20properties:
21  compatible:
22    const: samsung,exynos7-decon
23
24  clocks:
25    maxItems: 4
26
27  clock-names:
28    items:
29      - const: pclk_decon0
30      - const: aclk_decon0
31      - const: decon0_eclk
32      - const: decon0_vclk
33
34  display-timings:
35    $ref: ../panel/display-timings.yaml#
36
37  i80-if-timings:
38    type: object
39    additionalProperties: false
40    description: timing configuration for lcd i80 interface support
41    properties:
42      cs-setup:
43        $ref: /schemas/types.yaml#/definitions/uint32
44        description:
45          Clock cycles for the active period of address signal is enabled until
46          chip select is enabled.
47        default: 0
48
49      wr-active:
50        $ref: /schemas/types.yaml#/definitions/uint32
51        description:
52          Clock cycles for the active period of CS is enabled.
53        default: 1
54
55      wr-hold:
56        $ref: /schemas/types.yaml#/definitions/uint32
57        description:
58          Clock cycles for the active period of CS is disabled until write
59          signal is disabled.
60        default: 0
61
62      wr-setup:
63        $ref: /schemas/types.yaml#/definitions/uint32
64        description:
65          Clock cycles for the active period of CS signal is enabled until
66          write signal is enabled.
67        default: 0
68
69  interrupts:
70    items:
71      - description: FIFO level
72      - description: VSYNC
73      - description: LCD system
74
75  interrupt-names:
76    items:
77      - const: fifo
78      - const: vsync
79      - const: lcd_sys
80
81  power-domains:
82    maxItems: 1
83
84  reg:
85    maxItems: 1
86
87required:
88  - compatible
89  - clocks
90  - clock-names
91  - interrupts
92  - interrupt-names
93  - reg
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/clock/exynos7-clk.h>
100    #include <dt-bindings/interrupt-controller/arm-gic.h>
101
102    display-controller@13930000 {
103        compatible = "samsung,exynos7-decon";
104        reg = <0x13930000 0x1000>;
105        interrupt-names = "fifo", "vsync", "lcd_sys";
106        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
109        clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
110                 <&clock_disp 101>, /* ACLK_DECON_INT */
111                 <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
112                 <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
113        clock-names = "pclk_decon0",
114                      "aclk_decon0",
115                      "decon0_eclk",
116                      "decon0_vclk";
117        pinctrl-0 = <&lcd_clk &pwm1_out>;
118        pinctrl-names = "default";
119    };
120