1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON) 8 9maintainers: 10 - Inki Dae <inki.dae@samsung.com> 11 - Seung-Woo Kim <sw0312.kim@samsung.com> 12 - Kyungmin Park <kyungmin.park@samsung.com> 13 - Krzysztof Kozlowski <krzk@kernel.org> 14 15description: | 16 DECON (Display and Enhancement Controller) is the Display Controller for the 17 Exynos5433 series of SoCs which transfers the image data from a video memory 18 buffer to an external LCD interface. 19 20properties: 21 compatible: 22 enum: 23 - samsung,exynos5433-decon 24 - samsung,exynos5433-decon-tv 25 26 clocks: 27 minItems: 11 28 maxItems: 11 29 30 clock-names: 31 items: 32 - const: pclk 33 - const: aclk_decon 34 - const: aclk_smmu_decon0x 35 - const: aclk_xiu_decon0x 36 - const: pclk_smmu_decon0x 37 - const: aclk_smmu_decon1x 38 - const: aclk_xiu_decon1x 39 - const: pclk_smmu_decon1x 40 - const: sclk_decon_vclk 41 - const: sclk_decon_eclk 42 - const: dsd 43 44 interrupts: 45 minItems: 3 46 maxItems: 4 47 description: | 48 Interrupts depend on mode of work: 49 - video mode: vsync 50 - command mode: lcd_sys 51 - command mode with software trigger: lcd_sys, te 52 53 interrupt-names: 54 minItems: 3 55 items: 56 - const: fifo 57 - const: vsync 58 - const: lcd_sys 59 - const: te 60 61 iommus: 62 minItems: 2 63 maxItems: 2 64 65 iommu-names: 66 items: 67 - const: m0 68 - const: m1 69 70 ports: 71 $ref: /schemas/graph.yaml#/properties/ports 72 description: 73 Contains a port which is connected to mic node. 74 75 power-domains: 76 maxItems: 1 77 78 reg: 79 maxItems: 1 80 81 samsung,disp-sysreg: 82 $ref: /schemas/types.yaml#/definitions/phandle 83 description: 84 Phandle to DISP system controller interface. 85 86required: 87 - compatible 88 - clocks 89 - clock-names 90 - interrupts 91 - interrupt-names 92 - ports 93 - reg 94 95additionalProperties: false 96 97examples: 98 - | 99 #include <dt-bindings/clock/exynos5433.h> 100 #include <dt-bindings/interrupt-controller/arm-gic.h> 101 102 display-controller@13800000 { 103 compatible = "samsung,exynos5433-decon"; 104 reg = <0x13800000 0x2104>; 105 clocks = <&cmu_disp CLK_PCLK_DECON>, 106 <&cmu_disp CLK_ACLK_DECON>, 107 <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 108 <&cmu_disp CLK_ACLK_XIU_DECON0X>, 109 <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 110 <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 111 <&cmu_disp CLK_ACLK_XIU_DECON1X>, 112 <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 113 <&cmu_disp CLK_SCLK_DECON_VCLK>, 114 <&cmu_disp CLK_SCLK_DECON_ECLK>, 115 <&cmu_disp CLK_SCLK_DSD>; 116 clock-names = "pclk", 117 "aclk_decon", 118 "aclk_smmu_decon0x", 119 "aclk_xiu_decon0x", 120 "pclk_smmu_decon0x", 121 "aclk_smmu_decon1x", 122 "aclk_xiu_decon1x", 123 "pclk_smmu_decon1x", 124 "sclk_decon_vclk", 125 "sclk_decon_eclk", 126 "dsd"; 127 power-domains = <&pd_disp>; 128 interrupt-names = "fifo", "vsync", "lcd_sys"; 129 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 132 samsung,disp-sysreg = <&syscon_disp>; 133 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; 134 iommu-names = "m0", "m1"; 135 136 ports { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 port@0 { 141 reg = <0>; 142 decon_to_mic: endpoint { 143 remote-endpoint = <&mic_to_decon>; 144 }; 145 }; 146 }; 147 }; 148