xref: /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/rockchip-vop2.yaml (revision 370e009188ba90c3290b1479aa06ec98b66e140a) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC display controller (VOP2)
8
9description:
10  VOP2 (Video Output Processor v2) is the display controller for the Rockchip
11  series of SoCs which transfers the image data from a video memory
12  buffer to an external LCD interface.
13
14maintainers:
15  - Sandy Huang <hjc@rock-chips.com>
16  - Heiko Stuebner <heiko@sntech.de>
17
18properties:
19  compatible:
20    enum:
21      - rockchip,rk3566-vop
22      - rockchip,rk3568-vop
23
24  reg:
25    items:
26      - description:
27          Must contain one entry corresponding to the base address and length
28          of the register space.
29      - description:
30          Can optionally contain a second entry corresponding to
31          the CRTC gamma LUT address.
32
33  reg-names:
34    items:
35      - const: vop
36      - const: gamma-lut
37
38  interrupts:
39    maxItems: 1
40    description:
41      The VOP interrupt is shared by several interrupt sources, such as
42      frame start (VSYNC), line flag and other status interrupts.
43
44  clocks:
45    items:
46      - description: Clock for ddr buffer transfer.
47      - description: Clock for the ahb bus to R/W the phy regs.
48      - description: Pixel clock for video port 0.
49      - description: Pixel clock for video port 1.
50      - description: Pixel clock for video port 2.
51
52  clock-names:
53    items:
54      - const: aclk
55      - const: hclk
56      - const: dclk_vp0
57      - const: dclk_vp1
58      - const: dclk_vp2
59
60  rockchip,grf:
61    $ref: /schemas/types.yaml#/definitions/phandle
62    description:
63      Phandle to GRF regs used for misc control
64
65  ports:
66    $ref: /schemas/graph.yaml#/properties/ports
67
68    properties:
69      port@0:
70        $ref: /schemas/graph.yaml#/properties/port
71        description:
72          Output endpoint of VP0
73
74      port@1:
75        $ref: /schemas/graph.yaml#/properties/port
76        description:
77          Output endpoint of VP1
78
79      port@2:
80        $ref: /schemas/graph.yaml#/properties/port
81        description:
82          Output endpoint of VP2
83
84  iommus:
85    maxItems: 1
86
87  power-domains:
88    maxItems: 1
89
90required:
91  - compatible
92  - reg
93  - reg-names
94  - interrupts
95  - clocks
96  - clock-names
97  - ports
98
99additionalProperties: false
100
101examples:
102  - |
103        #include <dt-bindings/clock/rk3568-cru.h>
104        #include <dt-bindings/interrupt-controller/arm-gic.h>
105        #include <dt-bindings/power/rk3568-power.h>
106        bus {
107            #address-cells = <2>;
108            #size-cells = <2>;
109            vop: vop@fe040000 {
110                compatible = "rockchip,rk3568-vop";
111                reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
112                reg-names = "vop", "gamma-lut";
113                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
114                clocks = <&cru ACLK_VOP>,
115                         <&cru HCLK_VOP>,
116                         <&cru DCLK_VOP0>,
117                         <&cru DCLK_VOP1>,
118                         <&cru DCLK_VOP2>;
119                clock-names = "aclk",
120                              "hclk",
121                              "dclk_vp0",
122                              "dclk_vp1",
123                              "dclk_vp2";
124                power-domains = <&power RK3568_PD_VO>;
125                iommus = <&vop_mmu>;
126                vop_out: ports {
127                    #address-cells = <1>;
128                    #size-cells = <0>;
129                    vp0: port@0 {
130                        reg = <0>;
131                        #address-cells = <1>;
132                        #size-cells = <0>;
133                    };
134                    vp1: port@1 {
135                        reg = <1>;
136                        #address-cells = <1>;
137                        #size-cells = <0>;
138                    };
139                    vp2: port@2 {
140                        reg = <2>;
141                        #address-cells = <1>;
142                        #size-cells = <0>;
143                    };
144                };
145            };
146        };
147