xref: /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/rockchip,dw-hdmi.yaml (revision 2eb4d8dc723da3cf7d735a3226ae49da4c8c5dbc)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip DWC HDMI TX Encoder

maintainers:
  - Mark Yao <markyao0591@gmail.com>

description: |
  The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
  with a companion PHY IP.

allOf:
  - $ref: ../bridge/synopsys,dw-hdmi.yaml#

properties:
  compatible:
    enum:
      - rockchip,rk3228-dw-hdmi
      - rockchip,rk3288-dw-hdmi
      - rockchip,rk3328-dw-hdmi
      - rockchip,rk3399-dw-hdmi

  reg-io-width:
    const: 4

  clocks:
    minItems: 2
    maxItems: 5
    items:
      - {}
      - {}
      # The next three clocks are all optional, but shall be specified in this
      # order when present.
      - description: The HDMI CEC controller main clock
      - description: Power for GRF IO
      - description: External clock for some HDMI PHY

  clock-names:
    minItems: 2
    maxItems: 5
    items:
      - {}
      - {}
      - enum:
          - cec
          - grf
          - vpll
      - enum:
          - grf
          - vpll
      - const: vpll

  ddc-i2c-bus:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The HDMI DDC bus can be connected to either a system I2C master or the
      functionally-reduced I2C master contained in the DWC HDMI. When connected
      to a system I2C master this property contains a phandle to that I2C
      master controller.

  phys:
    maxItems: 1
    description: The HDMI PHY

  phy-names:
    const: hdmi

  pinctrl-names:
    description:
      The unwedge pinctrl entry shall drive the DDC SDA line low. This is
      intended to work around a hardware errata that can cause the DDC I2C
      bus to be wedged.
    items:
      - const: default
      - const: unwedge

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: Input of the DWC HDMI TX

        properties:
          endpoint@0:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Connection to the VOPB

          endpoint@1:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Connection to the VOPL

        required:
          - endpoint@0
          - endpoint@1

    required:
      - port

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the GRF to mux vopl/vopb.

required:
  - compatible
  - reg
  - reg-io-width
  - clocks
  - clock-names
  - interrupts
  - ports
  - rockchip,grf

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3288-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    hdmi: hdmi@ff980000 {
        compatible = "rockchip,rk3288-dw-hdmi";
        reg = <0xff980000 0x20000>;
        reg-io-width = <4>;
        ddc-i2c-bus = <&i2c5>;
        rockchip,grf = <&grf>;
        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
        clock-names = "iahb", "isfr";

        ports {
            port {
                #address-cells = <1>;
                #size-cells = <0>;

                hdmi_in_vopb: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&vopb_out_hdmi>;
                };
                hdmi_in_vopl: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&vopl_out_hdmi>;
                };
            };
        };
    };

...