xref: /freebsd/sys/contrib/device-tree/Bindings/display/renesas,rzg2l-du.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L Display Unit (DU)
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12
13description: |
14  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
15  and RZ/V2L SoCs.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - renesas,r9a07g043u-du # RZ/G2UL
22          - renesas,r9a07g044-du # RZ/G2{L,LC}
23          - renesas,r9a09g057-du # RZ/V2H(P)
24      - items:
25          - enum:
26              - renesas,r9a07g054-du    # RZ/V2L
27          - const: renesas,r9a07g044-du # RZ/G2L fallback
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  clocks:
36    items:
37      - description: Main clock
38      - description: Register access clock
39      - description: Video clock
40
41  clock-names:
42    items:
43      - const: aclk
44      - const: pclk
45      - const: vclk
46
47  resets:
48    maxItems: 1
49
50  power-domains:
51    maxItems: 1
52
53  ports:
54    $ref: /schemas/graph.yaml#/properties/ports
55    description: |
56      The connections to the DU output video ports are modeled using the OF
57      graph bindings. The number of ports and their assignment are
58      model-dependent. Each port shall have a single endpoint.
59
60    patternProperties:
61      "^port@[0-1]$":
62        $ref: /schemas/graph.yaml#/properties/port
63        unevaluatedProperties: false
64
65    unevaluatedProperties: false
66
67  renesas,vsps:
68    $ref: /schemas/types.yaml#/definitions/phandle-array
69    items:
70      items:
71        - description: phandle to VSP instance that serves the DU channel
72        - description: Channel index identifying the LIF instance in that VSP
73    description:
74      A list of phandle and channel index tuples to the VSPs that handle the
75      memory interfaces for the DU channels.
76
77required:
78  - compatible
79  - reg
80  - interrupts
81  - clocks
82  - clock-names
83  - resets
84  - power-domains
85  - ports
86  - renesas,vsps
87
88additionalProperties: false
89
90allOf:
91  - if:
92      properties:
93        compatible:
94          contains:
95            const: renesas,r9a07g043u-du
96    then:
97      properties:
98        ports:
99          properties:
100            port@0:
101              description: DPI
102
103          required:
104            - port@0
105  - if:
106      properties:
107        compatible:
108          contains:
109            const: renesas,r9a07g044-du
110    then:
111      properties:
112        ports:
113          properties:
114            port@0:
115              description: DSI
116            port@1:
117              description: DPI
118
119          required:
120            - port@0
121            - port@1
122  - if:
123      properties:
124        compatible:
125          contains:
126            const: renesas,r9a09g057-du
127    then:
128      properties:
129        ports:
130          properties:
131            port@0:
132              description: DSI
133            port@1: false
134
135          required:
136            - port@0
137
138examples:
139  # RZ/G2L DU
140  - |
141    #include <dt-bindings/clock/r9a07g044-cpg.h>
142    #include <dt-bindings/interrupt-controller/arm-gic.h>
143
144    display@10890000 {
145        compatible = "renesas,r9a07g044-du";
146        reg = <0x10890000 0x10000>;
147        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
148        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
149                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
150                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
151        clock-names = "aclk", "pclk", "vclk";
152        resets = <&cpg R9A07G044_LCDC_RESET_N>;
153        power-domains = <&cpg>;
154
155        renesas,vsps = <&vspd0 0>;
156
157        ports {
158            #address-cells = <1>;
159            #size-cells = <0>;
160
161            port@0 {
162                reg = <0>;
163                endpoint {
164                    remote-endpoint = <&dsi0_in>;
165                };
166            };
167            port@1 {
168                reg = <1>;
169            };
170        };
171    };
172
173...
174