1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MIPI DBI SPI Panel 8 9maintainers: 10 - Noralf Trønnes <noralf@tronnes.org> 11 12description: | 13 This binding is for display panels using a MIPI DBI compatible controller 14 in SPI mode. 15 16 The MIPI Alliance Standard for Display Bus Interface defines the electrical 17 and logical interfaces for display controllers historically used in mobile 18 phones. The standard defines 4 display architecture types and this binding is 19 for type 1 which has full frame memory. There are 3 interface types in the 20 standard and type C is the serial interface. 21 22 The standard defines the following interface signals for type C: 23 - Power: 24 - Vdd: Power supply for display module 25 Called power-supply in this binding. 26 - Vddi: Logic level supply for interface signals 27 Called io-supply in this binding. 28 - Interface: 29 - CSx: Chip select 30 - SCL: Serial clock 31 - Dout: Serial out 32 - Din: Serial in 33 - SDA: Bidrectional in/out 34 - D/CX: Data/command selection, high=data, low=command 35 Called dc-gpios in this binding. 36 - RESX: Reset when low 37 Called reset-gpios in this binding. 38 39 The type C interface has 3 options: 40 41 - Option 1: 9-bit mode and D/CX as the 9th bit 42 | Command | the next command or following data | 43 |<0><D7><D6><D5><D4><D3><D2><D1><D0>|<D/CX><D7><D6><D5><D4><D3><D2><D1><D0>| 44 45 - Option 2: 16-bit mode and D/CX as a 9th bit 46 | Command or data | 47 |<X><X><X><X><X><X><X><D/CX><D7><D6><D5><D4><D3><D2><D1><D0>| 48 49 - Option 3: 8-bit mode and D/CX as a separate interface line 50 | Command or data | 51 |<D7><D6><D5><D4><D3><D2><D1><D0>| 52 53 The panel resolution is specified using the panel-timing node properties 54 hactive (width) and vactive (height). The other mandatory panel-timing 55 properties should be set to zero except clock-frequency which can be 56 optionally set to inform about the actual pixel clock frequency. 57 58 If the panel is wired to the controller at an offset specify this using 59 hback-porch (x-offset) and vback-porch (y-offset). 60 61allOf: 62 - $ref: panel-common.yaml# 63 - $ref: /schemas/spi/spi-peripheral-props.yaml# 64 65properties: 66 compatible: 67 items: 68 - enum: 69 - sainsmart18 70 - const: panel-mipi-dbi-spi 71 72 write-only: 73 type: boolean 74 description: 75 Controller is not readable (ie. Din (MISO on the SPI interface) is not 76 wired up). 77 78 dc-gpios: 79 maxItems: 1 80 description: | 81 Controller data/command selection (D/CX) in 4-line SPI mode. 82 If not set, the controller is in 3-line SPI mode. 83 84 io-supply: 85 description: | 86 Logic level supply for interface signals (Vddi). 87 No need to set if this is the same as power-supply. 88 89required: 90 - compatible 91 - reg 92 - width-mm 93 - height-mm 94 - panel-timing 95 96unevaluatedProperties: false 97 98examples: 99 - | 100 #include <dt-bindings/gpio/gpio.h> 101 102 spi { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 display@0{ 107 compatible = "sainsmart18", "panel-mipi-dbi-spi"; 108 reg = <0>; 109 spi-max-frequency = <40000000>; 110 111 dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 112 reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 113 write-only; 114 115 backlight = <&backlight>; 116 117 width-mm = <35>; 118 height-mm = <28>; 119 120 panel-timing { 121 hactive = <160>; 122 vactive = <128>; 123 hback-porch = <0>; 124 vback-porch = <0>; 125 clock-frequency = <0>; 126 hfront-porch = <0>; 127 hsync-len = <0>; 128 vfront-porch = <0>; 129 vsync-len = <0>; 130 }; 131 }; 132 }; 133 134... 135