xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm8650-mdss.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8650 Display MDSS
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12description:
13  SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8650-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display core
27
28  iommus:
29    maxItems: 1
30
31  interconnects:
32    maxItems: 2
33
34  interconnect-names:
35    maxItems: 2
36
37patternProperties:
38  "^display-controller@[0-9a-f]+$":
39    type: object
40    properties:
41      compatible:
42        const: qcom,sm8650-dpu
43
44  "^displayport-controller@[0-9a-f]+$":
45    type: object
46    properties:
47      compatible:
48        const: qcom,sm8650-dp
49
50  "^dsi@[0-9a-f]+$":
51    type: object
52    properties:
53      compatible:
54        items:
55          - const: qcom,sm8650-dsi-ctrl
56          - const: qcom,mdss-dsi-ctrl
57
58  "^phy@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,sm8650-dsi-phy-4nm
63
64required:
65  - compatible
66
67unevaluatedProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,rpmh.h>
72    #include <dt-bindings/interrupt-controller/arm-gic.h>
73    #include <dt-bindings/power/qcom,rpmhpd.h>
74
75    display-subsystem@ae00000 {
76        compatible = "qcom,sm8650-mdss";
77        reg = <0x0ae00000 0x1000>;
78        reg-names = "mdss";
79
80        resets = <&dispcc_core_bcr>;
81
82        power-domains = <&dispcc_gdsc>;
83
84        clocks = <&gcc_ahb_clk>,
85                 <&gcc_axi_clk>,
86                 <&dispcc_mdp_clk>;
87        clock-names = "bus", "nrt_bus", "core";
88
89        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
90        interrupt-controller;
91        #interrupt-cells = <1>;
92
93        iommus = <&apps_smmu 0x1c00 0x2>;
94
95        #address-cells = <1>;
96        #size-cells = <1>;
97        ranges;
98
99        display-controller@ae01000 {
100            compatible = "qcom,sm8650-dpu";
101            reg = <0x0ae01000 0x8f000>,
102                  <0x0aeb0000 0x2008>;
103            reg-names = "mdp", "vbif";
104
105            clocks = <&gcc_axi_clk>,
106                     <&dispcc_ahb_clk>,
107                     <&dispcc_mdp_lut_clk>,
108                     <&dispcc_mdp_clk>,
109                     <&dispcc_mdp_vsync_clk>;
110            clock-names = "nrt_bus",
111                          "iface",
112                          "lut",
113                          "core",
114                          "vsync";
115
116            assigned-clocks = <&dispcc_mdp_vsync_clk>;
117            assigned-clock-rates = <19200000>;
118
119            operating-points-v2 = <&mdp_opp_table>;
120            power-domains = <&rpmhpd RPMHPD_MMCX>;
121
122            interrupt-parent = <&mdss>;
123            interrupts = <0>;
124
125            ports {
126                #address-cells = <1>;
127                #size-cells = <0>;
128
129                port@0 {
130                    reg = <0>;
131                    dpu_intf1_out: endpoint {
132                        remote-endpoint = <&dsi0_in>;
133                    };
134                };
135
136                port@1 {
137                    reg = <1>;
138                    dpu_intf2_out: endpoint {
139                        remote-endpoint = <&dsi1_in>;
140                    };
141                };
142            };
143
144            mdp_opp_table: opp-table {
145                compatible = "operating-points-v2";
146
147                opp-200000000 {
148                    opp-hz = /bits/ 64 <200000000>;
149                    required-opps = <&rpmhpd_opp_low_svs>;
150                };
151
152                opp-325000000 {
153                    opp-hz = /bits/ 64 <325000000>;
154                    required-opps = <&rpmhpd_opp_svs>;
155                };
156
157                opp-375000000 {
158                    opp-hz = /bits/ 64 <375000000>;
159                    required-opps = <&rpmhpd_opp_svs_l1>;
160                };
161
162                opp-514000000 {
163                    opp-hz = /bits/ 64 <514000000>;
164                    required-opps = <&rpmhpd_opp_nom>;
165                };
166            };
167        };
168
169        dsi@ae94000 {
170            compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
171            reg = <0x0ae94000 0x400>;
172            reg-names = "dsi_ctrl";
173
174            interrupt-parent = <&mdss>;
175            interrupts = <4>;
176
177            clocks = <&dispc_byte_clk>,
178                     <&dispcc_intf_clk>,
179                     <&dispcc_pclk>,
180                     <&dispcc_esc_clk>,
181                     <&dispcc_ahb_clk>,
182                     <&gcc_bus_clk>;
183            clock-names = "byte",
184                          "byte_intf",
185                          "pixel",
186                          "core",
187                          "iface",
188                          "bus";
189
190            assigned-clocks = <&dispcc_byte_clk>,
191                              <&dispcc_pclk>;
192            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
193
194            operating-points-v2 = <&dsi_opp_table>;
195            power-domains = <&rpmhpd RPMHPD_MMCX>;
196
197            phys = <&dsi0_phy>;
198            phy-names = "dsi";
199
200            #address-cells = <1>;
201            #size-cells = <0>;
202
203            ports {
204                #address-cells = <1>;
205                #size-cells = <0>;
206
207                port@0 {
208                    reg = <0>;
209                    dsi0_in: endpoint {
210                        remote-endpoint = <&dpu_intf1_out>;
211                    };
212                };
213
214                port@1 {
215                    reg = <1>;
216                    dsi0_out: endpoint {
217                    };
218                };
219            };
220
221            dsi_opp_table: opp-table {
222                compatible = "operating-points-v2";
223
224                opp-187500000 {
225                    opp-hz = /bits/ 64 <187500000>;
226                    required-opps = <&rpmhpd_opp_low_svs>;
227                };
228
229                opp-300000000 {
230                    opp-hz = /bits/ 64 <300000000>;
231                    required-opps = <&rpmhpd_opp_svs>;
232                };
233
234                opp-358000000 {
235                    opp-hz = /bits/ 64 <358000000>;
236                    required-opps = <&rpmhpd_opp_svs_l1>;
237                };
238            };
239        };
240
241        dsi0_phy: phy@ae94400 {
242            compatible = "qcom,sm8650-dsi-phy-4nm";
243            reg = <0x0ae95000 0x200>,
244                  <0x0ae95200 0x280>,
245                  <0x0ae95500 0x400>;
246            reg-names = "dsi_phy",
247                        "dsi_phy_lane",
248                        "dsi_pll";
249
250            #clock-cells = <1>;
251            #phy-cells = <0>;
252
253            clocks = <&dispcc_iface_clk>,
254                     <&rpmhcc_ref_clk>;
255            clock-names = "iface", "ref";
256        };
257
258        dsi@ae96000 {
259            compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
260            reg = <0x0ae96000 0x400>;
261            reg-names = "dsi_ctrl";
262
263            interrupt-parent = <&mdss>;
264            interrupts = <5>;
265
266            clocks = <&dispc_byte_clk>,
267                     <&dispcc_intf_clk>,
268                     <&dispcc_pclk>,
269                     <&dispcc_esc_clk>,
270                     <&dispcc_ahb_clk>,
271                     <&gcc_bus_clk>;
272            clock-names = "byte",
273                          "byte_intf",
274                          "pixel",
275                          "core",
276                          "iface",
277                          "bus";
278
279            assigned-clocks = <&dispcc_byte_clk>,
280                              <&dispcc_pclk>;
281            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
282
283            operating-points-v2 = <&dsi_opp_table>;
284            power-domains = <&rpmhpd RPMHPD_MMCX>;
285
286            phys = <&dsi1_phy>;
287            phy-names = "dsi";
288
289            #address-cells = <1>;
290            #size-cells = <0>;
291
292            ports {
293                #address-cells = <1>;
294                #size-cells = <0>;
295
296                port@0 {
297                    reg = <0>;
298                    dsi1_in: endpoint {
299                        remote-endpoint = <&dpu_intf2_out>;
300                    };
301                };
302
303                port@1 {
304                    reg = <1>;
305                    dsi1_out: endpoint {
306                    };
307                };
308            };
309        };
310
311        dsi1_phy: phy@ae96400 {
312            compatible = "qcom,sm8650-dsi-phy-4nm";
313            reg = <0x0ae97000 0x200>,
314                  <0x0ae97200 0x280>,
315                  <0x0ae97500 0x400>;
316            reg-names = "dsi_phy",
317                        "dsi_phy_lane",
318                        "dsi_pll";
319
320            #clock-cells = <1>;
321            #phy-cells = <0>;
322
323            clocks = <&dispcc_iface_clk>,
324                     <&rpmhcc_ref_clk>;
325            clock-names = "iface", "ref";
326        };
327    };
328...
329