xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm8650-dpu.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8650 Display DPU
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12$ref: /schemas/display/msm/dpu-common.yaml#
13
14properties:
15  compatible:
16    enum:
17      - qcom,sa8775p-dpu
18      - qcom,sm8650-dpu
19      - qcom,sm8750-dpu
20      - qcom,x1e80100-dpu
21
22  reg:
23    items:
24      - description: Address offset and size for mdp register set
25      - description: Address offset and size for vbif register set
26
27  reg-names:
28    items:
29      - const: mdp
30      - const: vbif
31
32  clocks:
33    items:
34      - description: Display hf axi
35      - description: Display MDSS ahb
36      - description: Display lut
37      - description: Display core
38      - description: Display vsync
39
40  clock-names:
41    items:
42      - const: nrt_bus
43      - const: iface
44      - const: lut
45      - const: core
46      - const: vsync
47
48required:
49  - compatible
50  - reg
51  - reg-names
52  - clocks
53  - clock-names
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/interrupt-controller/arm-gic.h>
60    #include <dt-bindings/power/qcom,rpmhpd.h>
61
62    display-controller@ae01000 {
63        compatible = "qcom,sm8650-dpu";
64        reg = <0x0ae01000 0x8f000>,
65              <0x0aeb0000 0x2008>;
66        reg-names = "mdp", "vbif";
67
68        clocks = <&gcc_axi_clk>,
69                 <&dispcc_ahb_clk>,
70                 <&dispcc_mdp_lut_clk>,
71                 <&dispcc_mdp_clk>,
72                 <&dispcc_vsync_clk>;
73        clock-names = "nrt_bus",
74                      "iface",
75                      "lut",
76                      "core",
77                      "vsync";
78
79        assigned-clocks = <&dispcc_vsync_clk>;
80        assigned-clock-rates = <19200000>;
81
82        operating-points-v2 = <&mdp_opp_table>;
83        power-domains = <&rpmhpd RPMHPD_MMCX>;
84
85        interrupt-parent = <&mdss>;
86        interrupts = <0>;
87
88        ports {
89            #address-cells = <1>;
90            #size-cells = <0>;
91
92            port@0 {
93                reg = <0>;
94                dpu_intf1_out: endpoint {
95                    remote-endpoint = <&dsi0_in>;
96                };
97            };
98
99            port@1 {
100                reg = <1>;
101                dpu_intf2_out: endpoint {
102                    remote-endpoint = <&dsi1_in>;
103                };
104            };
105        };
106
107        mdp_opp_table: opp-table {
108            compatible = "operating-points-v2";
109
110            opp-200000000 {
111                opp-hz = /bits/ 64 <200000000>;
112                required-opps = <&rpmhpd_opp_low_svs>;
113            };
114
115            opp-325000000 {
116                opp-hz = /bits/ 64 <325000000>;
117                required-opps = <&rpmhpd_opp_svs>;
118            };
119
120            opp-375000000 {
121                opp-hz = /bits/ 64 <375000000>;
122                required-opps = <&rpmhpd_opp_svs_l1>;
123            };
124
125            opp-514000000 {
126                opp-hz = /bits/ 64 <514000000>;
127                required-opps = <&rpmhpd_opp_nom>;
128            };
129        };
130    };
131...
132