xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm8550-mdss.yaml (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 Display MDSS
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12description:
13  SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8550-mdss
21
22  clocks:
23    items:
24      - description: Display MDSS AHB
25      - description: Display AHB
26      - description: Display hf AXI
27      - description: Display core
28
29  iommus:
30    maxItems: 1
31
32  interconnects:
33    maxItems: 2
34
35  interconnect-names:
36    maxItems: 2
37
38patternProperties:
39  "^display-controller@[0-9a-f]+$":
40    type: object
41    properties:
42      compatible:
43        const: qcom,sm8550-dpu
44
45  "^dsi@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        items:
50          - const: qcom,sm8550-dsi-ctrl
51          - const: qcom,mdss-dsi-ctrl
52
53  "^phy@[0-9a-f]+$":
54    type: object
55    properties:
56      compatible:
57        const: qcom,sm8550-dsi-phy-4nm
58
59required:
60  - compatible
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
67    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
68    #include <dt-bindings/clock/qcom,rpmh.h>
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
71    #include <dt-bindings/power/qcom-rpmpd.h>
72
73    display-subsystem@ae00000 {
74        compatible = "qcom,sm8550-mdss";
75        reg = <0x0ae00000 0x1000>;
76        reg-names = "mdss";
77
78        interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
79                        <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
80        interconnect-names = "mdp0-mem", "mdp1-mem";
81
82        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
83
84        power-domains = <&dispcc MDSS_GDSC>;
85
86        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
87                 <&gcc GCC_DISP_AHB_CLK>,
88                 <&gcc GCC_DISP_HF_AXI_CLK>,
89                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
90        clock-names = "iface", "bus", "nrt_bus", "core";
91
92        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
93        interrupt-controller;
94        #interrupt-cells = <1>;
95
96        iommus = <&apps_smmu 0x1c00 0x2>;
97
98        #address-cells = <1>;
99        #size-cells = <1>;
100        ranges;
101
102        display-controller@ae01000 {
103            compatible = "qcom,sm8550-dpu";
104            reg = <0x0ae01000 0x8f000>,
105                  <0x0aeb0000 0x2008>;
106            reg-names = "mdp", "vbif";
107
108            clocks = <&gcc GCC_DISP_AHB_CLK>,
109                    <&gcc GCC_DISP_HF_AXI_CLK>,
110                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
111                    <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
112                    <&dispcc DISP_CC_MDSS_MDP_CLK>,
113                    <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
114            clock-names = "bus",
115                          "nrt_bus",
116                          "iface",
117                          "lut",
118                          "core",
119                          "vsync";
120
121            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
122            assigned-clock-rates = <19200000>;
123
124            operating-points-v2 = <&mdp_opp_table>;
125            power-domains = <&rpmhpd SM8550_MMCX>;
126
127            interrupt-parent = <&mdss>;
128            interrupts = <0>;
129
130            ports {
131                #address-cells = <1>;
132                #size-cells = <0>;
133
134                port@0 {
135                    reg = <0>;
136                    dpu_intf1_out: endpoint {
137                        remote-endpoint = <&dsi0_in>;
138                    };
139                };
140
141                port@1 {
142                    reg = <1>;
143                    dpu_intf2_out: endpoint {
144                        remote-endpoint = <&dsi1_in>;
145                    };
146                };
147            };
148
149            mdp_opp_table: opp-table {
150                compatible = "operating-points-v2";
151
152                opp-200000000 {
153                    opp-hz = /bits/ 64 <200000000>;
154                    required-opps = <&rpmhpd_opp_low_svs>;
155                };
156
157                opp-325000000 {
158                    opp-hz = /bits/ 64 <325000000>;
159                    required-opps = <&rpmhpd_opp_svs>;
160                };
161
162                opp-375000000 {
163                    opp-hz = /bits/ 64 <375000000>;
164                    required-opps = <&rpmhpd_opp_svs_l1>;
165                };
166
167                opp-514000000 {
168                    opp-hz = /bits/ 64 <514000000>;
169                    required-opps = <&rpmhpd_opp_nom>;
170                };
171            };
172        };
173
174        dsi@ae94000 {
175            compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
176            reg = <0x0ae94000 0x400>;
177            reg-names = "dsi_ctrl";
178
179            interrupt-parent = <&mdss>;
180            interrupts = <4>;
181
182            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
183                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
184                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
185                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
186                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
187                     <&gcc GCC_DISP_HF_AXI_CLK>;
188            clock-names = "byte",
189                          "byte_intf",
190                          "pixel",
191                          "core",
192                          "iface",
193                          "bus";
194
195            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
196                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
197            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
198
199            operating-points-v2 = <&dsi_opp_table>;
200            power-domains = <&rpmhpd SM8550_MMCX>;
201
202            phys = <&dsi0_phy>;
203            phy-names = "dsi";
204
205            #address-cells = <1>;
206            #size-cells = <0>;
207
208            ports {
209                #address-cells = <1>;
210                #size-cells = <0>;
211
212                port@0 {
213                    reg = <0>;
214                    dsi0_in: endpoint {
215                        remote-endpoint = <&dpu_intf1_out>;
216                    };
217                };
218
219                port@1 {
220                    reg = <1>;
221                    dsi0_out: endpoint {
222                    };
223                };
224            };
225
226            dsi_opp_table: opp-table {
227                compatible = "operating-points-v2";
228
229                opp-187500000 {
230                    opp-hz = /bits/ 64 <187500000>;
231                    required-opps = <&rpmhpd_opp_low_svs>;
232                };
233
234                opp-300000000 {
235                    opp-hz = /bits/ 64 <300000000>;
236                    required-opps = <&rpmhpd_opp_svs>;
237                };
238
239                opp-358000000 {
240                    opp-hz = /bits/ 64 <358000000>;
241                    required-opps = <&rpmhpd_opp_svs_l1>;
242                };
243            };
244        };
245
246        dsi0_phy: phy@ae94400 {
247            compatible = "qcom,sm8550-dsi-phy-4nm";
248            reg = <0x0ae95000 0x200>,
249                  <0x0ae95200 0x280>,
250                  <0x0ae95500 0x400>;
251            reg-names = "dsi_phy",
252                        "dsi_phy_lane",
253                        "dsi_pll";
254
255            #clock-cells = <1>;
256            #phy-cells = <0>;
257
258            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
259                     <&rpmhcc RPMH_CXO_CLK>;
260            clock-names = "iface", "ref";
261        };
262
263        dsi@ae96000 {
264            compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
265            reg = <0x0ae96000 0x400>;
266            reg-names = "dsi_ctrl";
267
268            interrupt-parent = <&mdss>;
269            interrupts = <5>;
270
271            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
272                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
273                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
274                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
275                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
276                     <&gcc GCC_DISP_HF_AXI_CLK>;
277            clock-names = "byte",
278                          "byte_intf",
279                          "pixel",
280                          "core",
281                          "iface",
282                          "bus";
283
284            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
285                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
286            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
287
288            operating-points-v2 = <&dsi_opp_table>;
289            power-domains = <&rpmhpd SM8550_MMCX>;
290
291            phys = <&dsi1_phy>;
292            phy-names = "dsi";
293
294            #address-cells = <1>;
295            #size-cells = <0>;
296
297            ports {
298                #address-cells = <1>;
299                #size-cells = <0>;
300
301                port@0 {
302                    reg = <0>;
303                    dsi1_in: endpoint {
304                        remote-endpoint = <&dpu_intf2_out>;
305                    };
306                };
307
308                port@1 {
309                    reg = <1>;
310                    dsi1_out: endpoint {
311                    };
312                };
313            };
314        };
315
316        dsi1_phy: phy@ae96400 {
317            compatible = "qcom,sm8550-dsi-phy-4nm";
318            reg = <0x0ae97000 0x200>,
319                  <0x0ae97200 0x280>,
320                  <0x0ae97500 0x400>;
321            reg-names = "dsi_phy",
322                        "dsi_phy_lane",
323                        "dsi_pll";
324
325            #clock-cells = <1>;
326            #phy-cells = <0>;
327
328            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
329                     <&rpmhcc RPMH_CXO_CLK>;
330            clock-names = "iface", "ref";
331        };
332    };
333...
334