xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm8550-dpu.yaml (revision db33c6f3ae9d1231087710068ee4ea5398aacca7) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 Display DPU
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12$ref: /schemas/display/msm/dpu-common.yaml#
13
14properties:
15  compatible:
16    const: qcom,sm8550-dpu
17
18  reg:
19    items:
20      - description: Address offset and size for mdp register set
21      - description: Address offset and size for vbif register set
22
23  reg-names:
24    items:
25      - const: mdp
26      - const: vbif
27
28  clocks:
29    items:
30      - description: Display AHB
31      - description: Display hf axi
32      - description: Display MDSS ahb
33      - description: Display lut
34      - description: Display core
35      - description: Display vsync
36
37  clock-names:
38    items:
39      - const: bus
40      - const: nrt_bus
41      - const: iface
42      - const: lut
43      - const: core
44      - const: vsync
45
46required:
47  - compatible
48  - reg
49  - reg-names
50  - clocks
51  - clock-names
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
58    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
59    #include <dt-bindings/interrupt-controller/arm-gic.h>
60    #include <dt-bindings/power/qcom,rpmhpd.h>
61
62    display-controller@ae01000 {
63        compatible = "qcom,sm8550-dpu";
64        reg = <0x0ae01000 0x8f000>,
65              <0x0aeb0000 0x2008>;
66        reg-names = "mdp", "vbif";
67
68        clocks = <&gcc GCC_DISP_AHB_CLK>,
69                <&gcc GCC_DISP_HF_AXI_CLK>,
70                <&dispcc DISP_CC_MDSS_AHB_CLK>,
71                <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
72                <&dispcc DISP_CC_MDSS_MDP_CLK>,
73                <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
74        clock-names = "bus",
75                      "nrt_bus",
76                      "iface",
77                      "lut",
78                      "core",
79                      "vsync";
80
81        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
82        assigned-clock-rates = <19200000>;
83
84        operating-points-v2 = <&mdp_opp_table>;
85        power-domains = <&rpmhpd RPMHPD_MMCX>;
86
87        interrupt-parent = <&mdss>;
88        interrupts = <0>;
89
90        ports {
91            #address-cells = <1>;
92            #size-cells = <0>;
93
94            port@0 {
95                reg = <0>;
96                dpu_intf1_out: endpoint {
97                    remote-endpoint = <&dsi0_in>;
98                };
99            };
100
101            port@1 {
102                reg = <1>;
103                dpu_intf2_out: endpoint {
104                    remote-endpoint = <&dsi1_in>;
105                };
106            };
107        };
108
109        mdp_opp_table: opp-table {
110            compatible = "operating-points-v2";
111
112            opp-200000000 {
113                opp-hz = /bits/ 64 <200000000>;
114                required-opps = <&rpmhpd_opp_low_svs>;
115            };
116
117            opp-325000000 {
118                opp-hz = /bits/ 64 <325000000>;
119                required-opps = <&rpmhpd_opp_svs>;
120            };
121
122            opp-375000000 {
123                opp-hz = /bits/ 64 <375000000>;
124                required-opps = <&rpmhpd_opp_svs_l1>;
125            };
126
127            opp-514000000 {
128                opp-hz = /bits/ 64 <514000000>;
129                required-opps = <&rpmhpd_opp_nom>;
130            };
131        };
132    };
133...
134