xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm8350-mdss.yaml (revision 725a9f47324d42037db93c27ceb40d4956872f3e) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8350 Display MDSS
8
9maintainers:
10  - Robert Foss <robert.foss@linaro.org>
11
12description:
13  MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    items:
21      - const: qcom,sm8350-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display hf axi clock
27      - description: Display sf axi clock
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: bus
34      - const: nrt_bus
35      - const: core
36
37  iommus:
38    maxItems: 1
39
40  interconnects:
41    maxItems: 2
42
43  interconnect-names:
44    items:
45      - const: mdp0-mem
46      - const: mdp1-mem
47
48patternProperties:
49  "^display-controller@[0-9a-f]+$":
50    type: object
51    properties:
52      compatible:
53        const: qcom,sm8350-dpu
54
55  "^dsi@[0-9a-f]+$":
56    type: object
57    properties:
58      compatible:
59        items:
60          - const: qcom,sm8350-dsi-ctrl
61          - const: qcom,mdss-dsi-ctrl
62
63  "^phy@[0-9a-f]+$":
64    type: object
65    properties:
66      compatible:
67        const: qcom,sm8350-dsi-phy-5nm
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
74    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
75    #include <dt-bindings/clock/qcom,rpmh.h>
76    #include <dt-bindings/interrupt-controller/arm-gic.h>
77    #include <dt-bindings/interconnect/qcom,sm8350.h>
78    #include <dt-bindings/power/qcom-rpmpd.h>
79
80    display-subsystem@ae00000 {
81        compatible = "qcom,sm8350-mdss";
82        reg = <0x0ae00000 0x1000>;
83        reg-names = "mdss";
84
85        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
86                        <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
87        interconnect-names = "mdp0-mem", "mdp1-mem";
88
89        power-domains = <&dispcc MDSS_GDSC>;
90        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
91
92        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
93                 <&gcc GCC_DISP_HF_AXI_CLK>,
94                 <&gcc GCC_DISP_SF_AXI_CLK>,
95                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
96        clock-names = "iface", "bus", "nrt_bus", "core";
97
98        iommus = <&apps_smmu 0x820 0x402>;
99
100        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
101        interrupt-controller;
102        #interrupt-cells = <1>;
103
104        #address-cells = <1>;
105        #size-cells = <1>;
106        ranges;
107
108        display-controller@ae01000 {
109            compatible = "qcom,sm8350-dpu";
110            reg = <0x0ae01000 0x8f000>,
111                  <0x0aeb0000 0x2008>;
112            reg-names = "mdp", "vbif";
113
114            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
115                     <&gcc GCC_DISP_SF_AXI_CLK>,
116                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
117                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
118                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
119                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
120            clock-names = "bus",
121                          "nrt_bus",
122                          "iface",
123                          "lut",
124                          "core",
125                          "vsync";
126
127            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
128            assigned-clock-rates = <19200000>;
129
130            operating-points-v2 = <&mdp_opp_table>;
131            power-domains = <&rpmhpd SM8350_MMCX>;
132
133            interrupt-parent = <&mdss>;
134            interrupts = <0>;
135
136            ports {
137                #address-cells = <1>;
138                #size-cells = <0>;
139
140                port@0 {
141                    reg = <0>;
142                    dpu_intf1_out: endpoint {
143                        remote-endpoint = <&dsi0_in>;
144                    };
145                };
146            };
147
148            mdp_opp_table: opp-table {
149                compatible = "operating-points-v2";
150
151                opp-200000000 {
152                    opp-hz = /bits/ 64 <200000000>;
153                    required-opps = <&rpmhpd_opp_low_svs>;
154                };
155
156                opp-300000000 {
157                    opp-hz = /bits/ 64 <300000000>;
158                    required-opps = <&rpmhpd_opp_svs>;
159                };
160
161                opp-345000000 {
162                    opp-hz = /bits/ 64 <345000000>;
163                    required-opps = <&rpmhpd_opp_svs_l1>;
164                };
165
166                opp-460000000 {
167                    opp-hz = /bits/ 64 <460000000>;
168                    required-opps = <&rpmhpd_opp_nom>;
169                };
170            };
171        };
172
173        dsi0: dsi@ae94000 {
174            compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
175            reg = <0x0ae94000 0x400>;
176            reg-names = "dsi_ctrl";
177
178            interrupt-parent = <&mdss>;
179            interrupts = <4>;
180
181            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
182                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
183                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
184                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
185                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
186                     <&gcc GCC_DISP_HF_AXI_CLK>;
187            clock-names = "byte",
188                      "byte_intf",
189                      "pixel",
190                      "core",
191                      "iface",
192                      "bus";
193
194            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
195                          <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
196            assigned-clock-parents = <&mdss_dsi0_phy 0>,
197                                 <&mdss_dsi0_phy 1>;
198
199            operating-points-v2 = <&dsi_opp_table>;
200            power-domains = <&rpmhpd SM8350_MMCX>;
201
202            phys = <&mdss_dsi0_phy>;
203
204            ports {
205             #address-cells = <1>;
206                #size-cells = <0>;
207
208                port@0 {
209                    reg = <0>;
210                    dsi0_in: endpoint {
211                        remote-endpoint = <&dpu_intf1_out>;
212                    };
213                };
214
215                port@1 {
216                    reg = <1>;
217                    dsi0_out: endpoint {
218                    };
219                };
220            };
221        };
222    };
223...
224