xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm8250-mdss.yaml (revision 8bab661a3316d8bd9b9fbd11a3b4371b91507bd2) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8250 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SM8250 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,sm8250-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display hf axi clock
28      - description: Display sf axi clock
29      - description: Display core clock
30
31  clock-names:
32    items:
33      - const: iface
34      - const: bus
35      - const: nrt_bus
36      - const: core
37
38  iommus:
39    maxItems: 1
40
41  interconnects:
42    maxItems: 2
43
44  interconnect-names:
45    maxItems: 2
46
47patternProperties:
48  "^display-controller@[0-9a-f]+$":
49    type: object
50    properties:
51      compatible:
52        const: qcom,sm8250-dpu
53
54  "^dsi@[0-9a-f]+$":
55    type: object
56    properties:
57      compatible:
58        const: qcom,mdss-dsi-ctrl
59
60  "^phy@[0-9a-f]+$":
61    type: object
62    properties:
63      compatible:
64        const: qcom,dsi-phy-7nm
65
66unevaluatedProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
71    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
72    #include <dt-bindings/clock/qcom,rpmh.h>
73    #include <dt-bindings/interrupt-controller/arm-gic.h>
74    #include <dt-bindings/interconnect/qcom,sm8250.h>
75    #include <dt-bindings/power/qcom-rpmpd.h>
76
77    display-subsystem@ae00000 {
78        compatible = "qcom,sm8250-mdss";
79        reg = <0x0ae00000 0x1000>;
80        reg-names = "mdss";
81
82        interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
83                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
84        interconnect-names = "mdp0-mem", "mdp1-mem";
85
86        power-domains = <&dispcc MDSS_GDSC>;
87
88        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
89                 <&gcc GCC_DISP_HF_AXI_CLK>,
90                 <&gcc GCC_DISP_SF_AXI_CLK>,
91                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
92        clock-names = "iface", "bus", "nrt_bus", "core";
93
94        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
95        interrupt-controller;
96        #interrupt-cells = <1>;
97
98        iommus = <&apps_smmu 0x820 0x402>;
99
100        #address-cells = <1>;
101        #size-cells = <1>;
102        ranges;
103
104        display-controller@ae01000 {
105            compatible = "qcom,sm8250-dpu";
106            reg = <0x0ae01000 0x8f000>,
107                  <0x0aeb0000 0x2008>;
108            reg-names = "mdp", "vbif";
109
110            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
111                     <&gcc GCC_DISP_HF_AXI_CLK>,
112                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
113                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
114            clock-names = "iface", "bus", "core", "vsync";
115
116            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
117            assigned-clock-rates = <19200000>;
118
119            operating-points-v2 = <&mdp_opp_table>;
120            power-domains = <&rpmhpd SM8250_MMCX>;
121
122            interrupt-parent = <&mdss>;
123            interrupts = <0>;
124
125            ports {
126                #address-cells = <1>;
127                #size-cells = <0>;
128
129                port@0 {
130                    reg = <0>;
131                    dpu_intf1_out: endpoint {
132                        remote-endpoint = <&dsi0_in>;
133                    };
134                };
135
136                port@1 {
137                    reg = <1>;
138                    dpu_intf2_out: endpoint {
139                        remote-endpoint = <&dsi1_in>;
140                    };
141                };
142            };
143
144            mdp_opp_table: opp-table {
145                compatible = "operating-points-v2";
146
147                opp-200000000 {
148                    opp-hz = /bits/ 64 <200000000>;
149                    required-opps = <&rpmhpd_opp_low_svs>;
150                };
151
152                opp-300000000 {
153                    opp-hz = /bits/ 64 <300000000>;
154                    required-opps = <&rpmhpd_opp_svs>;
155                };
156
157                opp-345000000 {
158                    opp-hz = /bits/ 64 <345000000>;
159                    required-opps = <&rpmhpd_opp_svs_l1>;
160                };
161
162                opp-460000000 {
163                    opp-hz = /bits/ 64 <460000000>;
164                    required-opps = <&rpmhpd_opp_nom>;
165                };
166            };
167        };
168
169        dsi@ae94000 {
170            compatible = "qcom,mdss-dsi-ctrl";
171            reg = <0x0ae94000 0x400>;
172            reg-names = "dsi_ctrl";
173
174            interrupt-parent = <&mdss>;
175            interrupts = <4>;
176
177            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
178                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
179                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
180                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
181                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
182                     <&gcc GCC_DISP_HF_AXI_CLK>;
183            clock-names = "byte",
184                          "byte_intf",
185                          "pixel",
186                          "core",
187                          "iface",
188                          "bus";
189
190            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
191                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
192            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
193
194            operating-points-v2 = <&dsi_opp_table>;
195            power-domains = <&rpmhpd SM8250_MMCX>;
196
197            phys = <&dsi0_phy>;
198            phy-names = "dsi";
199
200            #address-cells = <1>;
201            #size-cells = <0>;
202
203            ports {
204                #address-cells = <1>;
205                #size-cells = <0>;
206
207                port@0 {
208                    reg = <0>;
209                    dsi0_in: endpoint {
210                        remote-endpoint = <&dpu_intf1_out>;
211                    };
212                };
213
214                port@1 {
215                    reg = <1>;
216                    dsi0_out: endpoint {
217                    };
218                };
219            };
220
221            dsi_opp_table: opp-table {
222                compatible = "operating-points-v2";
223
224                opp-187500000 {
225                    opp-hz = /bits/ 64 <187500000>;
226                    required-opps = <&rpmhpd_opp_low_svs>;
227                };
228
229                opp-300000000 {
230                    opp-hz = /bits/ 64 <300000000>;
231                    required-opps = <&rpmhpd_opp_svs>;
232                };
233
234                opp-358000000 {
235                    opp-hz = /bits/ 64 <358000000>;
236                    required-opps = <&rpmhpd_opp_svs_l1>;
237                };
238            };
239        };
240
241        dsi0_phy: phy@ae94400 {
242            compatible = "qcom,dsi-phy-7nm";
243            reg = <0x0ae94400 0x200>,
244                  <0x0ae94600 0x280>,
245                  <0x0ae94900 0x260>;
246            reg-names = "dsi_phy",
247                        "dsi_phy_lane",
248                        "dsi_pll";
249
250            #clock-cells = <1>;
251            #phy-cells = <0>;
252
253            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
254                     <&rpmhcc RPMH_CXO_CLK>;
255            clock-names = "iface", "ref";
256            vdds-supply = <&vreg_dsi_phy>;
257        };
258
259        dsi@ae96000 {
260            compatible = "qcom,mdss-dsi-ctrl";
261            reg = <0x0ae96000 0x400>;
262            reg-names = "dsi_ctrl";
263
264            interrupt-parent = <&mdss>;
265            interrupts = <5>;
266
267            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
268                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
269                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
270                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
271                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
272                     <&gcc GCC_DISP_HF_AXI_CLK>;
273            clock-names = "byte",
274                          "byte_intf",
275                          "pixel",
276                          "core",
277                          "iface",
278                          "bus";
279
280            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
281                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
282            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
283
284            operating-points-v2 = <&dsi_opp_table>;
285            power-domains = <&rpmhpd SM8250_MMCX>;
286
287            phys = <&dsi1_phy>;
288            phy-names = "dsi";
289
290            #address-cells = <1>;
291            #size-cells = <0>;
292
293            ports {
294                #address-cells = <1>;
295                #size-cells = <0>;
296
297                port@0 {
298                    reg = <0>;
299                    dsi1_in: endpoint {
300                        remote-endpoint = <&dpu_intf2_out>;
301                    };
302                };
303
304                port@1 {
305                    reg = <1>;
306                    dsi1_out: endpoint {
307                    };
308                };
309            };
310        };
311
312        dsi1_phy: phy@ae96400 {
313            compatible = "qcom,dsi-phy-7nm";
314            reg = <0x0ae96400 0x200>,
315                  <0x0ae96600 0x280>,
316                  <0x0ae96900 0x260>;
317            reg-names = "dsi_phy",
318                        "dsi_phy_lane",
319                        "dsi_pll";
320
321            #clock-cells = <1>;
322            #phy-cells = <0>;
323
324            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
325                     <&rpmhcc RPMH_CXO_CLK>;
326            clock-names = "iface", "ref";
327            vdds-supply = <&vreg_dsi_phy>;
328        };
329    };
330...
331