1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8250 Display MDSS 8 9maintainers: 10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 11 12description: 13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 15 bindings of MDSS are mentioned for SM8250 target. 16 17$ref: /schemas/display/msm/mdss-common.yaml# 18 19properties: 20 compatible: 21 const: qcom,sm8250-mdss 22 23 clocks: 24 items: 25 - description: Display AHB clock from gcc 26 - description: Display hf axi clock 27 - description: Display sf axi clock 28 - description: Display core clock 29 30 clock-names: 31 items: 32 - const: iface 33 - const: bus 34 - const: nrt_bus 35 - const: core 36 37 iommus: 38 maxItems: 1 39 40 interconnects: 41 maxItems: 2 42 43 interconnect-names: 44 maxItems: 2 45 46patternProperties: 47 "^display-controller@[0-9a-f]+$": 48 type: object 49 properties: 50 compatible: 51 const: qcom,sm8250-dpu 52 53 "^dsi@[0-9a-f]+$": 54 type: object 55 properties: 56 compatible: 57 items: 58 - const: qcom,sm8250-dsi-ctrl 59 - const: qcom,mdss-dsi-ctrl 60 61 "^phy@[0-9a-f]+$": 62 type: object 63 properties: 64 compatible: 65 const: qcom,dsi-phy-7nm 66 67required: 68 - compatible 69 70unevaluatedProperties: false 71 72examples: 73 - | 74 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 75 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 76 #include <dt-bindings/clock/qcom,rpmh.h> 77 #include <dt-bindings/interrupt-controller/arm-gic.h> 78 #include <dt-bindings/interconnect/qcom,sm8250.h> 79 #include <dt-bindings/power/qcom-rpmpd.h> 80 81 display-subsystem@ae00000 { 82 compatible = "qcom,sm8250-mdss"; 83 reg = <0x0ae00000 0x1000>; 84 reg-names = "mdss"; 85 86 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 87 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 88 interconnect-names = "mdp0-mem", "mdp1-mem"; 89 90 power-domains = <&dispcc MDSS_GDSC>; 91 92 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 93 <&gcc GCC_DISP_HF_AXI_CLK>, 94 <&gcc GCC_DISP_SF_AXI_CLK>, 95 <&dispcc DISP_CC_MDSS_MDP_CLK>; 96 clock-names = "iface", "bus", "nrt_bus", "core"; 97 98 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-controller; 100 #interrupt-cells = <1>; 101 102 iommus = <&apps_smmu 0x820 0x402>; 103 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges; 107 108 display-controller@ae01000 { 109 compatible = "qcom,sm8250-dpu"; 110 reg = <0x0ae01000 0x8f000>, 111 <0x0aeb0000 0x2008>; 112 reg-names = "mdp", "vbif"; 113 114 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 115 <&gcc GCC_DISP_HF_AXI_CLK>, 116 <&dispcc DISP_CC_MDSS_MDP_CLK>, 117 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 118 clock-names = "iface", "bus", "core", "vsync"; 119 120 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 121 assigned-clock-rates = <19200000>; 122 123 operating-points-v2 = <&mdp_opp_table>; 124 power-domains = <&rpmhpd SM8250_MMCX>; 125 126 interrupt-parent = <&mdss>; 127 interrupts = <0>; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 port@0 { 134 reg = <0>; 135 dpu_intf1_out: endpoint { 136 remote-endpoint = <&dsi0_in>; 137 }; 138 }; 139 140 port@1 { 141 reg = <1>; 142 dpu_intf2_out: endpoint { 143 remote-endpoint = <&dsi1_in>; 144 }; 145 }; 146 }; 147 148 mdp_opp_table: opp-table { 149 compatible = "operating-points-v2"; 150 151 opp-200000000 { 152 opp-hz = /bits/ 64 <200000000>; 153 required-opps = <&rpmhpd_opp_low_svs>; 154 }; 155 156 opp-300000000 { 157 opp-hz = /bits/ 64 <300000000>; 158 required-opps = <&rpmhpd_opp_svs>; 159 }; 160 161 opp-345000000 { 162 opp-hz = /bits/ 64 <345000000>; 163 required-opps = <&rpmhpd_opp_svs_l1>; 164 }; 165 166 opp-460000000 { 167 opp-hz = /bits/ 64 <460000000>; 168 required-opps = <&rpmhpd_opp_nom>; 169 }; 170 }; 171 }; 172 173 dsi@ae94000 { 174 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 175 reg = <0x0ae94000 0x400>; 176 reg-names = "dsi_ctrl"; 177 178 interrupt-parent = <&mdss>; 179 interrupts = <4>; 180 181 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 182 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 183 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 184 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 185 <&dispcc DISP_CC_MDSS_AHB_CLK>, 186 <&gcc GCC_DISP_HF_AXI_CLK>; 187 clock-names = "byte", 188 "byte_intf", 189 "pixel", 190 "core", 191 "iface", 192 "bus"; 193 194 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 195 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 196 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 197 198 operating-points-v2 = <&dsi_opp_table>; 199 power-domains = <&rpmhpd SM8250_MMCX>; 200 201 phys = <&dsi0_phy>; 202 phy-names = "dsi"; 203 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 ports { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 211 port@0 { 212 reg = <0>; 213 dsi0_in: endpoint { 214 remote-endpoint = <&dpu_intf1_out>; 215 }; 216 }; 217 218 port@1 { 219 reg = <1>; 220 dsi0_out: endpoint { 221 }; 222 }; 223 }; 224 225 dsi_opp_table: opp-table { 226 compatible = "operating-points-v2"; 227 228 opp-187500000 { 229 opp-hz = /bits/ 64 <187500000>; 230 required-opps = <&rpmhpd_opp_low_svs>; 231 }; 232 233 opp-300000000 { 234 opp-hz = /bits/ 64 <300000000>; 235 required-opps = <&rpmhpd_opp_svs>; 236 }; 237 238 opp-358000000 { 239 opp-hz = /bits/ 64 <358000000>; 240 required-opps = <&rpmhpd_opp_svs_l1>; 241 }; 242 }; 243 }; 244 245 dsi0_phy: phy@ae94400 { 246 compatible = "qcom,dsi-phy-7nm"; 247 reg = <0x0ae94400 0x200>, 248 <0x0ae94600 0x280>, 249 <0x0ae94900 0x260>; 250 reg-names = "dsi_phy", 251 "dsi_phy_lane", 252 "dsi_pll"; 253 254 #clock-cells = <1>; 255 #phy-cells = <0>; 256 257 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 258 <&rpmhcc RPMH_CXO_CLK>; 259 clock-names = "iface", "ref"; 260 vdds-supply = <&vreg_dsi_phy>; 261 }; 262 263 dsi@ae96000 { 264 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 265 reg = <0x0ae96000 0x400>; 266 reg-names = "dsi_ctrl"; 267 268 interrupt-parent = <&mdss>; 269 interrupts = <5>; 270 271 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 272 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 273 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 274 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 275 <&dispcc DISP_CC_MDSS_AHB_CLK>, 276 <&gcc GCC_DISP_HF_AXI_CLK>; 277 clock-names = "byte", 278 "byte_intf", 279 "pixel", 280 "core", 281 "iface", 282 "bus"; 283 284 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 285 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 286 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 287 288 operating-points-v2 = <&dsi_opp_table>; 289 power-domains = <&rpmhpd SM8250_MMCX>; 290 291 phys = <&dsi1_phy>; 292 phy-names = "dsi"; 293 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 ports { 298 #address-cells = <1>; 299 #size-cells = <0>; 300 301 port@0 { 302 reg = <0>; 303 dsi1_in: endpoint { 304 remote-endpoint = <&dpu_intf2_out>; 305 }; 306 }; 307 308 port@1 { 309 reg = <1>; 310 dsi1_out: endpoint { 311 }; 312 }; 313 }; 314 }; 315 316 dsi1_phy: phy@ae96400 { 317 compatible = "qcom,dsi-phy-7nm"; 318 reg = <0x0ae96400 0x200>, 319 <0x0ae96600 0x280>, 320 <0x0ae96900 0x260>; 321 reg-names = "dsi_phy", 322 "dsi_phy_lane", 323 "dsi_pll"; 324 325 #clock-cells = <1>; 326 #phy-cells = <0>; 327 328 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 329 <&rpmhcc RPMH_CXO_CLK>; 330 clock-names = "iface", "ref"; 331 vdds-supply = <&vreg_dsi_phy>; 332 }; 333 }; 334... 335