xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm6375-mdss.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6375 Display MDSS
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@linaro.org>
11
12description:
13  SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14  like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6375-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AHB clock
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: ahb
32      - const: core
33
34  iommus:
35    maxItems: 1
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    properties:
47      compatible:
48        const: qcom,sm6375-dpu
49
50  "^dsi@[0-9a-f]+$":
51    type: object
52    properties:
53      compatible:
54        items:
55          - const: qcom,sm6375-dsi-ctrl
56          - const: qcom,mdss-dsi-ctrl
57
58  "^phy@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,sm6375-dsi-phy-7nm
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/qcom,rpmcc.h>
69    #include <dt-bindings/clock/qcom,sm6375-gcc.h>
70    #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72    #include <dt-bindings/power/qcom-rpmpd.h>
73
74    display-subsystem@5e00000 {
75        compatible = "qcom,sm6375-mdss";
76        reg = <0x05e00000 0x1000>;
77        reg-names = "mdss";
78
79        power-domains = <&dispcc MDSS_GDSC>;
80
81        clocks = <&gcc GCC_DISP_AHB_CLK>,
82                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
83                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
84        clock-names = "iface", "ahb", "core";
85
86        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
87        interrupt-controller;
88        #interrupt-cells = <1>;
89
90        iommus = <&apps_smmu 0x820 0x2>;
91        #address-cells = <1>;
92        #size-cells = <1>;
93        ranges;
94
95        display-controller@5e01000 {
96            compatible = "qcom,sm6375-dpu";
97            reg = <0x05e01000 0x8e030>,
98                  <0x05eb0000 0x2008>;
99            reg-names = "mdp", "vbif";
100
101            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
102                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
103                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
104                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
105                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
106                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
107                     <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
108            clock-names = "bus",
109                          "iface",
110                          "rot",
111                          "lut",
112                          "core",
113                          "vsync",
114                          "throttle";
115
116            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
117            assigned-clock-rates = <19200000>;
118
119            operating-points-v2 = <&mdp_opp_table>;
120            power-domains = <&rpmpd SM6375_VDDCX>;
121
122            interrupt-parent = <&mdss>;
123            interrupts = <0>;
124
125            ports {
126                #address-cells = <1>;
127                #size-cells = <0>;
128
129                port@0 {
130                    reg = <0>;
131                    dpu_intf1_out: endpoint {
132                        remote-endpoint = <&dsi0_in>;
133                    };
134                };
135
136                port@1 {
137                    reg = <1>;
138                    dpu_intf2_out: endpoint {
139                        remote-endpoint = <&dsi1_in>;
140                    };
141                };
142            };
143        };
144
145        dsi@5e94000 {
146            compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
147            reg = <0x05e94000 0x400>;
148            reg-names = "dsi_ctrl";
149
150            interrupt-parent = <&mdss>;
151            interrupts = <4>;
152
153            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
154                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
155                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
156                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
157                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
158                     <&gcc GCC_DISP_HF_AXI_CLK>;
159            clock-names = "byte",
160                          "byte_intf",
161                          "pixel",
162                          "core",
163                          "iface",
164                          "bus";
165
166            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
167                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
168            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
169
170            operating-points-v2 = <&dsi_opp_table>;
171            power-domains = <&rpmpd SM6375_VDDMX>;
172
173            phys = <&mdss_dsi0_phy>;
174            phy-names = "dsi";
175
176            #address-cells = <1>;
177            #size-cells = <0>;
178
179            ports {
180                #address-cells = <1>;
181                #size-cells = <0>;
182
183                port@0 {
184                    reg = <0>;
185                    dsi0_in: endpoint {
186                        remote-endpoint = <&dpu_intf1_out>;
187                    };
188                };
189
190                port@1 {
191                    reg = <1>;
192                    dsi0_out: endpoint {
193                    };
194                };
195            };
196        };
197
198        mdss_dsi0_phy: phy@5e94400 {
199            compatible = "qcom,sm6375-dsi-phy-7nm";
200            reg = <0x05e94400 0x200>,
201                  <0x05e94600 0x280>,
202                  <0x05e94900 0x264>;
203            reg-names = "dsi_phy",
204                        "dsi_phy_lane",
205                        "dsi_pll";
206
207            #clock-cells = <1>;
208            #phy-cells = <0>;
209
210            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
211                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
212            clock-names = "iface", "ref";
213        };
214    };
215...
216