xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm6350-mdss.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6350 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14  like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6350-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AXI clock from gcc
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: bus
32      - const: core
33
34  iommus:
35    maxItems: 1
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    properties:
47      compatible:
48        const: qcom,sm6350-dpu
49
50  "^dsi@[0-9a-f]+$":
51    type: object
52    properties:
53      compatible:
54        items:
55          - const: qcom,sm6350-dsi-ctrl
56          - const: qcom,mdss-dsi-ctrl
57
58  "^phy@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,dsi-phy-10nm
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
69    #include <dt-bindings/clock/qcom,gcc-sm6350.h>
70    #include <dt-bindings/clock/qcom,rpmh.h>
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72    #include <dt-bindings/power/qcom-rpmpd.h>
73
74    display-subsystem@ae00000 {
75        compatible = "qcom,sm6350-mdss";
76        reg = <0x0ae00000 0x1000>;
77        reg-names = "mdss";
78
79        power-domains = <&dispcc MDSS_GDSC>;
80
81        clocks = <&gcc GCC_DISP_AHB_CLK>,
82                 <&gcc GCC_DISP_AXI_CLK>,
83                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
84        clock-names = "iface", "bus", "core";
85
86        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
87        interrupt-controller;
88        #interrupt-cells = <1>;
89
90        iommus = <&apps_smmu 0x800 0x2>;
91        #address-cells = <1>;
92        #size-cells = <1>;
93        ranges;
94
95        display-controller@ae01000 {
96            compatible = "qcom,sm6350-dpu";
97            reg = <0x0ae01000 0x8f000>,
98                  <0x0aeb0000 0x2008>;
99            reg-names = "mdp", "vbif";
100
101            clocks = <&gcc GCC_DISP_AXI_CLK>,
102              <&dispcc DISP_CC_MDSS_AHB_CLK>,
103              <&dispcc DISP_CC_MDSS_ROT_CLK>,
104              <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
105              <&dispcc DISP_CC_MDSS_MDP_CLK>,
106              <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
107            clock-names = "bus", "iface", "rot", "lut", "core",
108                    "vsync";
109
110            assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
111                              <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
112                              <&dispcc DISP_CC_MDSS_ROT_CLK>,
113                              <&dispcc DISP_CC_MDSS_AHB_CLK>;
114            assigned-clock-rates = <300000000>,
115                                   <19200000>,
116                                   <19200000>,
117                                   <19200000>;
118
119            interrupt-parent = <&mdss>;
120            interrupts = <0>;
121            operating-points-v2 = <&mdp_opp_table>;
122            power-domains = <&rpmhpd SM6350_CX>;
123
124            ports {
125                #address-cells = <1>;
126                #size-cells = <0>;
127
128                port@0 {
129                    reg = <0>;
130                    dpu_intf1_out: endpoint {
131                        remote-endpoint = <&dsi0_in>;
132                    };
133                };
134
135                port@1 {
136                    reg = <1>;
137                    dpu_intf2_out: endpoint {
138                        remote-endpoint = <&dsi1_in>;
139                    };
140                };
141            };
142        };
143
144        dsi@ae94000 {
145            compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
146            reg = <0x0ae94000 0x400>;
147            reg-names = "dsi_ctrl";
148
149            interrupt-parent = <&mdss>;
150            interrupts = <4>;
151
152            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
153                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
154                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
155                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
156                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
157                     <&gcc GCC_DISP_AXI_CLK>;
158            clock-names = "byte",
159                          "byte_intf",
160                          "pixel",
161                          "core",
162                          "iface",
163                          "bus";
164
165            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
166                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
167            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
168
169            operating-points-v2 = <&dsi_opp_table>;
170            power-domains = <&rpmhpd SM6350_MX>;
171
172            phys = <&dsi0_phy>;
173            phy-names = "dsi";
174
175            #address-cells = <1>;
176            #size-cells = <0>;
177
178            ports {
179                #address-cells = <1>;
180                #size-cells = <0>;
181
182                port@0 {
183                    reg = <0>;
184                    dsi0_in: endpoint {
185                        remote-endpoint = <&dpu_intf1_out>;
186                    };
187                };
188
189                port@1 {
190                    reg = <1>;
191                    dsi0_out: endpoint {
192                    };
193                };
194            };
195        };
196
197        dsi0_phy: phy@ae94400 {
198            compatible = "qcom,dsi-phy-10nm";
199            reg = <0x0ae94400 0x200>,
200                  <0x0ae94600 0x280>,
201                  <0x0ae94a00 0x1e0>;
202            reg-names = "dsi_phy",
203                        "dsi_phy_lane",
204                        "dsi_pll";
205
206            #clock-cells = <1>;
207            #phy-cells = <0>;
208
209            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
210            clock-names = "iface", "ref";
211        };
212    };
213...
214