xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sm6115-mdss.yaml (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6115 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for SM6115 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm6115-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AXI clock
27      - description: Display core clock
28
29  iommus:
30    maxItems: 2
31
32patternProperties:
33  "^display-controller@[0-9a-f]+$":
34    type: object
35    properties:
36      compatible:
37        const: qcom,sm6115-dpu
38
39  "^dsi@[0-9a-f]+$":
40    type: object
41    properties:
42      compatible:
43        oneOf:
44          - items:
45              - const: qcom,sm6115-dsi-ctrl
46              - const: qcom,mdss-dsi-ctrl
47          - description: Old binding, please don't use
48            deprecated: true
49            const: qcom,dsi-ctrl-6g-qcm2290
50
51  "^phy@[0-9a-f]+$":
52    type: object
53    properties:
54      compatible:
55        const: qcom,dsi-phy-14nm-2290
56
57required:
58  - compatible
59
60unevaluatedProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
65    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
66    #include <dt-bindings/clock/qcom,rpmcc.h>
67    #include <dt-bindings/interrupt-controller/arm-gic.h>
68    #include <dt-bindings/power/qcom-rpmpd.h>
69
70    display-subsystem@5e00000 {
71        #address-cells = <1>;
72        #size-cells = <1>;
73        compatible = "qcom,sm6115-mdss";
74        reg = <0x05e00000 0x1000>;
75        reg-names = "mdss";
76        power-domains = <&dispcc MDSS_GDSC>;
77        clocks = <&gcc GCC_DISP_AHB_CLK>,
78                 <&gcc GCC_DISP_HF_AXI_CLK>,
79                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
80
81        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
82        interrupt-controller;
83        #interrupt-cells = <1>;
84
85        iommus = <&apps_smmu 0x420 0x2>,
86                 <&apps_smmu 0x421 0x0>;
87        ranges;
88
89        display-controller@5e01000 {
90            compatible = "qcom,sm6115-dpu";
91            reg = <0x05e01000 0x8f000>,
92                  <0x05eb0000 0x2008>;
93            reg-names = "mdp", "vbif";
94
95            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
96                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
97                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
98                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
99                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
100                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
101            clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
102
103            operating-points-v2 = <&mdp_opp_table>;
104            power-domains = <&rpmpd SM6115_VDDCX>;
105
106            interrupt-parent = <&mdss>;
107            interrupts = <0>;
108
109            ports {
110                #address-cells = <1>;
111                #size-cells = <0>;
112
113                port@0 {
114                    reg = <0>;
115                    dpu_intf1_out: endpoint {
116                        remote-endpoint = <&dsi0_in>;
117                    };
118                };
119            };
120        };
121
122        dsi@5e94000 {
123            compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
124            reg = <0x05e94000 0x400>;
125            reg-names = "dsi_ctrl";
126
127            interrupt-parent = <&mdss>;
128            interrupts = <4>;
129
130            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
131                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
132                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
133                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
134                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
135                     <&gcc GCC_DISP_HF_AXI_CLK>;
136            clock-names = "byte",
137                          "byte_intf",
138                          "pixel",
139                          "core",
140                          "iface",
141                          "bus";
142            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
143            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
144
145            operating-points-v2 = <&dsi_opp_table>;
146            power-domains = <&rpmpd SM6115_VDDCX>;
147            phys = <&dsi0_phy>;
148
149            #address-cells = <1>;
150            #size-cells = <0>;
151
152            ports {
153                #address-cells = <1>;
154                #size-cells = <0>;
155
156                port@0 {
157                    reg = <0>;
158                    dsi0_in: endpoint {
159                        remote-endpoint = <&dpu_intf1_out>;
160                    };
161                };
162
163                port@1 {
164                    reg = <1>;
165                    dsi0_out: endpoint {
166                    };
167                };
168            };
169        };
170
171        dsi0_phy: phy@5e94400 {
172            compatible = "qcom,dsi-phy-14nm-2290";
173            reg = <0x05e94400 0x100>,
174                  <0x05e94500 0x300>,
175                  <0x05e94800 0x188>;
176            reg-names = "dsi_phy",
177                        "dsi_phy_lane",
178                        "dsi_pll";
179
180            #clock-cells = <1>;
181            #phy-cells = <0>;
182
183            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
184            clock-names = "iface", "ref";
185        };
186    };
187...
188