xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sdm845-mdss.yaml (revision cb7aa33ac6cd46a5434798e50363136e64f3ae98) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM845 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SDM845 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sdm845-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: core
32
33  iommus:
34    maxItems: 2
35
36  interconnects:
37    maxItems: 2
38
39  interconnect-names:
40    maxItems: 2
41
42patternProperties:
43  "^display-controller@[0-9a-f]+$":
44    type: object
45    properties:
46      compatible:
47        const: qcom,sdm845-dpu
48
49  "^displayport-controller@[0-9a-f]+$":
50    type: object
51    properties:
52      compatible:
53        const: qcom,sdm845-dp
54
55  "^dsi@[0-9a-f]+$":
56    type: object
57    properties:
58      compatible:
59        items:
60          - const: qcom,sdm845-dsi-ctrl
61          - const: qcom,mdss-dsi-ctrl
62
63  "^phy@[0-9a-f]+$":
64    type: object
65    properties:
66      compatible:
67        const: qcom,dsi-phy-10nm
68
69required:
70  - compatible
71
72unevaluatedProperties: false
73
74examples:
75  - |
76    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
77    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
78    #include <dt-bindings/clock/qcom,rpmh.h>
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80    #include <dt-bindings/power/qcom-rpmpd.h>
81
82    display-subsystem@ae00000 {
83        #address-cells = <1>;
84        #size-cells = <1>;
85        compatible = "qcom,sdm845-mdss";
86        reg = <0x0ae00000 0x1000>;
87        reg-names = "mdss";
88        power-domains = <&dispcc MDSS_GDSC>;
89
90        clocks = <&gcc GCC_DISP_AHB_CLK>,
91                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
92        clock-names = "iface", "core";
93
94        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
95        interrupt-controller;
96        #interrupt-cells = <1>;
97
98        iommus = <&apps_smmu 0x880 0x8>,
99                 <&apps_smmu 0xc80 0x8>;
100        ranges;
101
102        display-controller@ae01000 {
103            compatible = "qcom,sdm845-dpu";
104            reg = <0x0ae01000 0x8f000>,
105                  <0x0aeb0000 0x2008>;
106            reg-names = "mdp", "vbif";
107
108            clocks = <&gcc GCC_DISP_AXI_CLK>,
109                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
110                     <&dispcc DISP_CC_MDSS_AXI_CLK>,
111                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
112                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
113            clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
114
115            interrupt-parent = <&mdss>;
116            interrupts = <0>;
117            power-domains = <&rpmhpd SDM845_CX>;
118            operating-points-v2 = <&mdp_opp_table>;
119
120            ports {
121                #address-cells = <1>;
122                #size-cells = <0>;
123
124                port@0 {
125                    reg = <0>;
126                    dpu_intf1_out: endpoint {
127                        remote-endpoint = <&dsi0_in>;
128                    };
129                };
130
131                port@1 {
132                    reg = <1>;
133                    dpu_intf2_out: endpoint {
134                        remote-endpoint = <&dsi1_in>;
135                    };
136                };
137            };
138        };
139
140        dsi@ae94000 {
141            compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
142            reg = <0x0ae94000 0x400>;
143            reg-names = "dsi_ctrl";
144
145            interrupt-parent = <&mdss>;
146            interrupts = <4>;
147
148            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
149                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
150                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
151                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
152                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
153                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
154            clock-names = "byte",
155                          "byte_intf",
156                          "pixel",
157                          "core",
158                          "iface",
159                          "bus";
160            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
161                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
162            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
163
164            operating-points-v2 = <&dsi_opp_table>;
165            power-domains = <&rpmhpd SDM845_CX>;
166
167            phys = <&dsi0_phy>;
168            phy-names = "dsi";
169
170            #address-cells = <1>;
171            #size-cells = <0>;
172
173            ports {
174                #address-cells = <1>;
175                #size-cells = <0>;
176
177                port@0 {
178                    reg = <0>;
179                    dsi0_in: endpoint {
180                        remote-endpoint = <&dpu_intf1_out>;
181                    };
182                };
183
184                port@1 {
185                    reg = <1>;
186                    dsi0_out: endpoint {
187                    };
188                };
189            };
190        };
191
192        dsi0_phy: phy@ae94400 {
193            compatible = "qcom,dsi-phy-10nm";
194            reg = <0x0ae94400 0x200>,
195                  <0x0ae94600 0x280>,
196                  <0x0ae94a00 0x1e0>;
197            reg-names = "dsi_phy",
198                        "dsi_phy_lane",
199                        "dsi_pll";
200
201            #clock-cells = <1>;
202            #phy-cells = <0>;
203
204            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
205                     <&rpmhcc RPMH_CXO_CLK>;
206            clock-names = "iface", "ref";
207            vdds-supply = <&vreg_dsi_phy>;
208        };
209
210        dsi@ae96000 {
211            compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
212            reg = <0x0ae96000 0x400>;
213            reg-names = "dsi_ctrl";
214
215            interrupt-parent = <&mdss>;
216            interrupts = <5>;
217
218            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
219                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
220                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
221                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
222                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
223                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
224            clock-names = "byte",
225                          "byte_intf",
226                          "pixel",
227                          "core",
228                          "iface",
229                          "bus";
230            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
231                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
232            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
233
234            operating-points-v2 = <&dsi_opp_table>;
235            power-domains = <&rpmhpd SDM845_CX>;
236
237            phys = <&dsi1_phy>;
238            phy-names = "dsi";
239
240            #address-cells = <1>;
241            #size-cells = <0>;
242
243            ports {
244                #address-cells = <1>;
245                #size-cells = <0>;
246
247                port@0 {
248                    reg = <0>;
249                    dsi1_in: endpoint {
250                        remote-endpoint = <&dpu_intf2_out>;
251                    };
252                };
253
254                port@1 {
255                    reg = <1>;
256                    dsi1_out: endpoint {
257                    };
258                };
259            };
260        };
261
262        dsi1_phy: phy@ae96400 {
263            compatible = "qcom,dsi-phy-10nm";
264            reg = <0x0ae96400 0x200>,
265                  <0x0ae96600 0x280>,
266                  <0x0ae96a00 0x10e>;
267            reg-names = "dsi_phy",
268                        "dsi_phy_lane",
269                        "dsi_pll";
270
271            #clock-cells = <1>;
272            #phy-cells = <0>;
273
274            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
275                     <&rpmhcc RPMH_CXO_CLK>;
276            clock-names = "iface", "ref";
277            vdds-supply = <&vreg_dsi_phy>;
278        };
279    };
280...
281