1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DPU on SDM845 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12$ref: /schemas/display/msm/dpu-common.yaml# 13 14properties: 15 compatible: 16 const: qcom,sdm845-dpu 17 18 reg: 19 items: 20 - description: Address offset and size for mdp register set 21 - description: Address offset and size for vbif register set 22 23 reg-names: 24 items: 25 - const: mdp 26 - const: vbif 27 28 clocks: 29 items: 30 - description: Display GCC bus clock 31 - description: Display ahb clock 32 - description: Display axi clock 33 - description: Display core clock 34 - description: Display vsync clock 35 36 clock-names: 37 items: 38 - const: gcc-bus 39 - const: iface 40 - const: bus 41 - const: core 42 - const: vsync 43 44required: 45 - compatible 46 - reg 47 - reg-names 48 - clocks 49 - clock-names 50 51unevaluatedProperties: false 52 53examples: 54 - | 55 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 56 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 57 #include <dt-bindings/power/qcom-rpmpd.h> 58 59 display-controller@ae01000 { 60 compatible = "qcom,sdm845-dpu"; 61 reg = <0x0ae01000 0x8f000>, 62 <0x0aeb0000 0x2008>; 63 reg-names = "mdp", "vbif"; 64 65 clocks = <&gcc GCC_DISP_AXI_CLK>, 66 <&dispcc DISP_CC_MDSS_AHB_CLK>, 67 <&dispcc DISP_CC_MDSS_AXI_CLK>, 68 <&dispcc DISP_CC_MDSS_MDP_CLK>, 69 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 70 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 71 72 interrupt-parent = <&mdss>; 73 interrupts = <0>; 74 power-domains = <&rpmhpd SDM845_CX>; 75 operating-points-v2 = <&mdp_opp_table>; 76 77 ports { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 port@0 { 82 reg = <0>; 83 endpoint { 84 remote-endpoint = <&dsi0_in>; 85 }; 86 }; 87 88 port@1 { 89 reg = <1>; 90 endpoint { 91 remote-endpoint = <&dsi1_in>; 92 }; 93 }; 94 }; 95 }; 96... 97