xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sc7280-mdss.yaml (revision d0b2dbfa0ecf2bbc9709efc5e20baf8e4b44bbbf) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7280 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC7280.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sc7280-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AHB clock from dispcc
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: ahb
33      - const: core
34
35  iommus:
36    maxItems: 1
37
38  interconnects:
39    maxItems: 1
40
41  interconnect-names:
42    maxItems: 1
43
44patternProperties:
45  "^display-controller@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        const: qcom,sc7280-dpu
50
51  "^displayport-controller@[0-9a-f]+$":
52    type: object
53    properties:
54      compatible:
55        const: qcom,sc7280-dp
56
57  "^dsi@[0-9a-f]+$":
58    type: object
59    properties:
60      compatible:
61        items:
62          - const: qcom,sc7280-dsi-ctrl
63          - const: qcom,mdss-dsi-ctrl
64
65  "^edp@[0-9a-f]+$":
66    type: object
67    properties:
68      compatible:
69        const: qcom,sc7280-edp
70
71  "^phy@[0-9a-f]+$":
72    type: object
73    properties:
74      compatible:
75        enum:
76          - qcom,sc7280-dsi-phy-7nm
77          - qcom,sc7280-edp-phy
78
79required:
80  - compatible
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
87    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
88    #include <dt-bindings/clock/qcom,rpmh.h>
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90    #include <dt-bindings/interconnect/qcom,sc7280.h>
91    #include <dt-bindings/power/qcom-rpmpd.h>
92
93    display-subsystem@ae00000 {
94        #address-cells = <1>;
95        #size-cells = <1>;
96        compatible = "qcom,sc7280-mdss";
97        reg = <0xae00000 0x1000>;
98        reg-names = "mdss";
99        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
100        clocks = <&gcc GCC_DISP_AHB_CLK>,
101                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
102                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
103        clock-names = "iface",
104                      "ahb",
105                      "core";
106
107        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
108        interrupt-controller;
109        #interrupt-cells = <1>;
110
111        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
112        interconnect-names = "mdp0-mem";
113
114        iommus = <&apps_smmu 0x900 0x402>;
115        ranges;
116
117        display-controller@ae01000 {
118            compatible = "qcom,sc7280-dpu";
119            reg = <0x0ae01000 0x8f000>,
120                  <0x0aeb0000 0x2008>;
121
122            reg-names = "mdp", "vbif";
123
124            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
125                     <&gcc GCC_DISP_SF_AXI_CLK>,
126                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
127                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
129                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130            clock-names = "bus",
131                          "nrt_bus",
132                          "iface",
133                          "lut",
134                          "core",
135                          "vsync";
136
137            interrupt-parent = <&mdss>;
138            interrupts = <0>;
139            power-domains = <&rpmhpd SC7280_CX>;
140            operating-points-v2 = <&mdp_opp_table>;
141
142            ports {
143                #address-cells = <1>;
144                #size-cells = <0>;
145
146                port@0 {
147                    reg = <0>;
148                    dpu_intf1_out: endpoint {
149                        remote-endpoint = <&dsi0_in>;
150                    };
151                };
152
153                port@1 {
154                    reg = <1>;
155                    dpu_intf5_out: endpoint {
156                        remote-endpoint = <&edp_in>;
157                    };
158                };
159
160                port@2 {
161                    reg = <2>;
162                    dpu_intf0_out: endpoint {
163                        remote-endpoint = <&dp_in>;
164                    };
165                };
166            };
167        };
168
169        dsi@ae94000 {
170            compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
171            reg = <0x0ae94000 0x400>;
172            reg-names = "dsi_ctrl";
173
174            interrupt-parent = <&mdss>;
175            interrupts = <4>;
176
177            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
178                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
179                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
180                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
181                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
182                     <&gcc GCC_DISP_HF_AXI_CLK>;
183            clock-names = "byte",
184                          "byte_intf",
185                          "pixel",
186                          "core",
187                          "iface",
188                          "bus";
189
190            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
191                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
192            assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
193
194            operating-points-v2 = <&dsi_opp_table>;
195            power-domains = <&rpmhpd SC7280_CX>;
196
197            phys = <&mdss_dsi_phy>;
198            phy-names = "dsi";
199
200            #address-cells = <1>;
201            #size-cells = <0>;
202
203            ports {
204                #address-cells = <1>;
205                #size-cells = <0>;
206
207                port@0 {
208                    reg = <0>;
209                    dsi0_in: endpoint {
210                        remote-endpoint = <&dpu_intf1_out>;
211                    };
212                };
213
214                port@1 {
215                    reg = <1>;
216                    dsi0_out: endpoint {
217                    };
218                };
219            };
220
221            dsi_opp_table: opp-table {
222                compatible = "operating-points-v2";
223
224                opp-187500000 {
225                    opp-hz = /bits/ 64 <187500000>;
226                    required-opps = <&rpmhpd_opp_low_svs>;
227                };
228
229                opp-300000000 {
230                    opp-hz = /bits/ 64 <300000000>;
231                    required-opps = <&rpmhpd_opp_svs>;
232                };
233
234                opp-358000000 {
235                    opp-hz = /bits/ 64 <358000000>;
236                    required-opps = <&rpmhpd_opp_svs_l1>;
237                };
238            };
239        };
240
241        mdss_dsi_phy: phy@ae94400 {
242            compatible = "qcom,sc7280-dsi-phy-7nm";
243            reg = <0x0ae94400 0x200>,
244                  <0x0ae94600 0x280>,
245                  <0x0ae94900 0x280>;
246            reg-names = "dsi_phy",
247                        "dsi_phy_lane",
248                        "dsi_pll";
249
250            #clock-cells = <1>;
251            #phy-cells = <0>;
252
253            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
254                     <&rpmhcc RPMH_CXO_CLK>;
255            clock-names = "iface", "ref";
256
257            vdds-supply = <&vreg_dsi_supply>;
258        };
259
260        edp@aea0000 {
261            compatible = "qcom,sc7280-edp";
262            pinctrl-names = "default";
263            pinctrl-0 = <&edp_hot_plug_det>;
264
265            reg = <0xaea0000 0x200>,
266                  <0xaea0200 0x200>,
267                  <0xaea0400 0xc00>,
268                  <0xaea1000 0x400>;
269
270            interrupt-parent = <&mdss>;
271            interrupts = <14>;
272
273            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
274                     <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
275                     <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
276                     <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
277                     <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
278            clock-names = "core_iface",
279                          "core_aux",
280                          "ctrl_link",
281                          "ctrl_link_iface",
282                          "stream_pixel";
283            assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
284                              <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
285            assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
286
287            phys = <&mdss_edp_phy>;
288            phy-names = "dp";
289
290            operating-points-v2 = <&edp_opp_table>;
291            power-domains = <&rpmhpd SC7280_CX>;
292
293            ports {
294                #address-cells = <1>;
295                #size-cells = <0>;
296
297                port@0 {
298                    reg = <0>;
299                    edp_in: endpoint {
300                        remote-endpoint = <&dpu_intf5_out>;
301                    };
302                };
303
304                port@1 {
305                    reg = <1>;
306                    mdss_edp_out: endpoint { };
307                };
308            };
309
310            edp_opp_table: opp-table {
311                compatible = "operating-points-v2";
312
313                opp-160000000 {
314                    opp-hz = /bits/ 64 <160000000>;
315                    required-opps = <&rpmhpd_opp_low_svs>;
316                };
317
318                opp-270000000 {
319                    opp-hz = /bits/ 64 <270000000>;
320                    required-opps = <&rpmhpd_opp_svs>;
321                };
322
323                opp-540000000 {
324                    opp-hz = /bits/ 64 <540000000>;
325                    required-opps = <&rpmhpd_opp_nom>;
326                };
327
328                opp-810000000 {
329                    opp-hz = /bits/ 64 <810000000>;
330                    required-opps = <&rpmhpd_opp_nom>;
331                };
332            };
333        };
334
335        mdss_edp_phy: phy@aec2a00 {
336            compatible = "qcom,sc7280-edp-phy";
337
338            reg = <0xaec2a00 0x19c>,
339                  <0xaec2200 0xa0>,
340                  <0xaec2600 0xa0>,
341                  <0xaec2000 0x1c0>;
342
343            clocks = <&rpmhcc RPMH_CXO_CLK>,
344                     <&gcc GCC_EDP_CLKREF_EN>;
345            clock-names = "aux",
346                          "cfg_ahb";
347
348            #clock-cells = <1>;
349            #phy-cells = <0>;
350        };
351
352        displayport-controller@ae90000 {
353            compatible = "qcom,sc7280-dp";
354
355            reg = <0xae90000 0x200>,
356                  <0xae90200 0x200>,
357                  <0xae90400 0xc00>,
358                  <0xae91000 0x400>,
359                  <0xae91400 0x400>;
360
361            interrupt-parent = <&mdss>;
362            interrupts = <12>;
363
364            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
365                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
366                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
367                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
368                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
369            clock-names = "core_iface",
370                          "core_aux",
371                          "ctrl_link",
372                          "ctrl_link_iface",
373                          "stream_pixel";
374            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
375                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
376            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
377            phys = <&dp_phy>;
378            phy-names = "dp";
379
380            operating-points-v2 = <&dp_opp_table>;
381            power-domains = <&rpmhpd SC7280_CX>;
382
383            #sound-dai-cells = <0>;
384
385            ports {
386                #address-cells = <1>;
387                #size-cells = <0>;
388
389                port@0 {
390                    reg = <0>;
391                    dp_in: endpoint {
392                        remote-endpoint = <&dpu_intf0_out>;
393                    };
394                };
395
396                port@1 {
397                    reg = <1>;
398                    dp_out: endpoint { };
399                };
400            };
401
402            dp_opp_table: opp-table {
403                compatible = "operating-points-v2";
404
405                opp-160000000 {
406                    opp-hz = /bits/ 64 <160000000>;
407                    required-opps = <&rpmhpd_opp_low_svs>;
408                };
409
410                opp-270000000 {
411                    opp-hz = /bits/ 64 <270000000>;
412                    required-opps = <&rpmhpd_opp_svs>;
413                };
414
415                opp-540000000 {
416                    opp-hz = /bits/ 64 <540000000>;
417                    required-opps = <&rpmhpd_opp_svs_l1>;
418                };
419
420                opp-810000000 {
421                    opp-hz = /bits/ 64 <810000000>;
422                    required-opps = <&rpmhpd_opp_nom>;
423                };
424            };
425        };
426    };
427...
428