xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/qcom,sc7180-mdss.yaml (revision 525fe93dc7487a1e63a90f6a2b956abc601963c1) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7180 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC7180 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sc7180-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AHB clock from dispcc
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: ahb
33      - const: core
34
35  iommus:
36    maxItems: 1
37
38  interconnects:
39    maxItems: 1
40
41  interconnect-names:
42    maxItems: 1
43
44patternProperties:
45  "^display-controller@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        const: qcom,sc7180-dpu
50
51  "^displayport-controller@[0-9a-f]+$":
52    type: object
53    properties:
54      compatible:
55        const: qcom,sc7180-dp
56
57  "^dsi@[0-9a-f]+$":
58    type: object
59    properties:
60      compatible:
61        items:
62          - const: qcom,sc7180-dsi-ctrl
63          - const: qcom,mdss-dsi-ctrl
64
65  "^phy@[0-9a-f]+$":
66    type: object
67    properties:
68      compatible:
69        const: qcom,dsi-phy-10nm
70
71required:
72  - compatible
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
79    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
80    #include <dt-bindings/clock/qcom,rpmh.h>
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/interconnect/qcom,sdm845.h>
83    #include <dt-bindings/power/qcom-rpmpd.h>
84
85    display-subsystem@ae00000 {
86        #address-cells = <1>;
87        #size-cells = <1>;
88        compatible = "qcom,sc7180-mdss";
89        reg = <0xae00000 0x1000>;
90        reg-names = "mdss";
91        power-domains = <&dispcc MDSS_GDSC>;
92        clocks = <&gcc GCC_DISP_AHB_CLK>,
93                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
94                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
95        clock-names = "iface", "ahb", "core";
96
97        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
98        interrupt-controller;
99        #interrupt-cells = <1>;
100
101        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
102        interconnect-names = "mdp0-mem";
103
104        iommus = <&apps_smmu 0x800 0x2>;
105        ranges;
106
107        display-controller@ae01000 {
108            compatible = "qcom,sc7180-dpu";
109            reg = <0x0ae01000 0x8f000>,
110                  <0x0aeb0000 0x2008>;
111
112            reg-names = "mdp", "vbif";
113
114            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
115                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
116                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
117                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
118                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
119                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
120            clock-names = "bus", "iface", "rot", "lut", "core",
121                          "vsync";
122
123            interrupt-parent = <&mdss>;
124            interrupts = <0>;
125            power-domains = <&rpmhpd SC7180_CX>;
126            operating-points-v2 = <&mdp_opp_table>;
127
128            ports {
129                #address-cells = <1>;
130                #size-cells = <0>;
131
132                port@0 {
133                    reg = <0>;
134                    dpu_intf1_out: endpoint {
135                        remote-endpoint = <&dsi0_in>;
136                    };
137                };
138
139                port@2 {
140                    reg = <2>;
141                    dpu_intf0_out: endpoint {
142                        remote-endpoint = <&dp_in>;
143                    };
144                };
145            };
146        };
147
148        dsi@ae94000 {
149            compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
150            reg = <0x0ae94000 0x400>;
151            reg-names = "dsi_ctrl";
152
153            interrupt-parent = <&mdss>;
154            interrupts = <4>;
155
156            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
159                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
160                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
161                     <&gcc GCC_DISP_HF_AXI_CLK>;
162            clock-names = "byte",
163                          "byte_intf",
164                          "pixel",
165                          "core",
166                          "iface",
167                          "bus";
168
169            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
170            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
171
172            operating-points-v2 = <&dsi_opp_table>;
173            power-domains = <&rpmhpd SC7180_CX>;
174
175            phys = <&dsi_phy>;
176            phy-names = "dsi";
177
178            #address-cells = <1>;
179            #size-cells = <0>;
180
181            ports {
182                #address-cells = <1>;
183                #size-cells = <0>;
184
185                port@0 {
186                    reg = <0>;
187                    dsi0_in: endpoint {
188                        remote-endpoint = <&dpu_intf1_out>;
189                    };
190                };
191
192                port@1 {
193                    reg = <1>;
194                    dsi0_out: endpoint {
195                    };
196                };
197            };
198
199            dsi_opp_table: opp-table {
200                compatible = "operating-points-v2";
201
202                opp-187500000 {
203                    opp-hz = /bits/ 64 <187500000>;
204                    required-opps = <&rpmhpd_opp_low_svs>;
205                };
206
207                opp-300000000 {
208                    opp-hz = /bits/ 64 <300000000>;
209                    required-opps = <&rpmhpd_opp_svs>;
210                };
211
212                opp-358000000 {
213                    opp-hz = /bits/ 64 <358000000>;
214                    required-opps = <&rpmhpd_opp_svs_l1>;
215                };
216            };
217        };
218
219        dsi_phy: phy@ae94400 {
220            compatible = "qcom,dsi-phy-10nm";
221            reg = <0x0ae94400 0x200>,
222                  <0x0ae94600 0x280>,
223                  <0x0ae94a00 0x1e0>;
224            reg-names = "dsi_phy",
225                    "dsi_phy_lane",
226                    "dsi_pll";
227
228            #clock-cells = <1>;
229            #phy-cells = <0>;
230
231            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
232                 <&rpmhcc RPMH_CXO_CLK>;
233            clock-names = "iface", "ref";
234            vdds-supply = <&vreg_dsi_phy>;
235        };
236
237        displayport-controller@ae90000 {
238            compatible = "qcom,sc7180-dp";
239
240            reg = <0xae90000 0x200>,
241                  <0xae90200 0x200>,
242                  <0xae90400 0xc00>,
243                  <0xae91000 0x400>,
244                  <0xae91400 0x400>;
245
246            interrupt-parent = <&mdss>;
247            interrupts = <12>;
248
249            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
250                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
251                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
252                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
253                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
254            clock-names = "core_iface", "core_aux", "ctrl_link",
255                          "ctrl_link_iface", "stream_pixel";
256            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
257                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
258            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
259            phys = <&dp_phy>;
260            phy-names = "dp";
261
262            operating-points-v2 = <&dp_opp_table>;
263            power-domains = <&rpmhpd SC7180_CX>;
264
265            #sound-dai-cells = <0>;
266
267            ports {
268                #address-cells = <1>;
269                #size-cells = <0>;
270                port@0 {
271                    reg = <0>;
272                    dp_in: endpoint {
273                        remote-endpoint = <&dpu_intf0_out>;
274                    };
275                };
276
277                port@1 {
278                    reg = <1>;
279                    dp_out: endpoint { };
280                };
281            };
282
283            dp_opp_table: opp-table {
284                compatible = "operating-points-v2";
285
286                opp-160000000 {
287                    opp-hz = /bits/ 64 <160000000>;
288                    required-opps = <&rpmhpd_opp_low_svs>;
289                };
290
291                opp-270000000 {
292                    opp-hz = /bits/ 64 <270000000>;
293                    required-opps = <&rpmhpd_opp_svs>;
294                };
295
296                opp-540000000 {
297                    opp-hz = /bits/ 64 <540000000>;
298                    required-opps = <&rpmhpd_opp_svs_l1>;
299                };
300
301                opp-810000000 {
302                    opp-hz = /bits/ 64 <810000000>;
303                    required-opps = <&rpmhpd_opp_nom>;
304                };
305            };
306        };
307    };
308...
309