xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/mdp5.txt (revision 02e9120893770924227138ba49df1edb3896112a) 
1Qualcomm adreno/snapdragon MDP5 display controller
2
3Description:
4
5This is the bindings documentation for the MDP5 display
6controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
7
8MDP5:
9Required properties:
10- compatible:
11  * "qcom,mdp5" - MDP5
12- reg: Physical base address and length of the controller's registers.
13- reg-names: The names of register regions. The following regions are required:
14  * "mdp_phys"
15- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
16- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
17- clock-names: the following clocks are required.
18-   * "bus"
19-   * "iface"
20-   * "core"
21-   * "vsync"
22- ports: contains the list of output ports from MDP. These connect to interfaces
23  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
24  special case since it is a part of the MDP block itself).
25
26  Each output port contains an endpoint that describes how it is connected to an
27  external interface. These are described by the standard properties documented
28  here:
29	Documentation/devicetree/bindings/graph.txt
30	Documentation/devicetree/bindings/media/video-interfaces.txt
31
32  The availability of output ports can vary across SoC revisions:
33
34  For MSM8974 and APQ8084:
35	 Port 0 -> MDP_INTF0 (eDP)
36	 Port 1 -> MDP_INTF1 (DSI1)
37	 Port 2 -> MDP_INTF2 (DSI2)
38	 Port 3 -> MDP_INTF3 (HDMI)
39
40  For MSM8916:
41	 Port 0 -> MDP_INTF1 (DSI1)
42
43  For MSM8994 and MSM8996:
44	 Port 0 -> MDP_INTF1 (DSI1)
45	 Port 1 -> MDP_INTF2 (DSI2)
46	 Port 2 -> MDP_INTF3 (HDMI)
47
48Optional properties:
49- clock-names: the following clocks are optional:
50  * "lut"
51  * "tbu"
52  * "tbu_rt"
53
54Example:
55
56/ {
57	...
58
59	mdss: mdss@1a00000 {
60		compatible = "qcom,mdss";
61		reg = <0x1a00000 0x1000>,
62		      <0x1ac8000 0x3000>;
63		reg-names = "mdss_phys", "vbif_phys";
64
65		power-domains = <&gcc MDSS_GDSC>;
66
67		clocks = <&gcc GCC_MDSS_AHB_CLK>,
68			 <&gcc GCC_MDSS_AXI_CLK>,
69			 <&gcc GCC_MDSS_VSYNC_CLK>;
70		clock-names = "iface",
71			      "bus",
72			      "vsync"
73
74		interrupts = <0 72 0>;
75
76		interrupt-controller;
77		#interrupt-cells = <1>;
78
79		#address-cells = <1>;
80		#size-cells = <1>;
81		ranges;
82
83		mdp: mdp@1a01000 {
84			compatible = "qcom,mdp5";
85			reg = <0x1a01000 0x90000>;
86			reg-names = "mdp_phys";
87
88			interrupt-parent = <&mdss>;
89			interrupts = <0 0>;
90
91			clocks = <&gcc GCC_MDSS_AHB_CLK>,
92				 <&gcc GCC_MDSS_AXI_CLK>,
93				 <&gcc GCC_MDSS_MDP_CLK>,
94				 <&gcc GCC_MDSS_VSYNC_CLK>;
95			clock-names = "iface",
96				      "bus",
97				      "core",
98				      "vsync";
99
100			ports {
101				#address-cells = <1>;
102				#size-cells = <0>;
103
104				port@0 {
105					reg = <0>;
106					mdp5_intf1_out: endpoint {
107						remote-endpoint = <&dsi0_in>;
108					};
109				};
110			};
111		};
112
113		dsi0: dsi@1a98000 {
114			...
115			ports {
116				...
117				port@0 {
118					reg = <0>;
119					dsi0_in: endpoint {
120						remote-endpoint = <&mdp5_intf1_out>;
121					};
122				};
123				...
124			};
125			...
126		};
127
128		dsi_phy0: dsi-phy@1a98300 {
129			...
130		};
131	};
132};
133