1Qualcomm adreno/snapdragon GPU 2 3Required properties: 4- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or 5 "amd,imageon-XYZ.W", "amd,imageon" 6 for example: "qcom,adreno-306.0", "qcom,adreno" 7 Note that you need to list the less specific "qcom,adreno" (since this 8 is what the device is matched on), in addition to the more specific 9 with the chip-id. 10 If "amd,imageon" is used, there should be no top level msm device. 11- reg: Physical base address and length of the controller's registers. 12- interrupts: The interrupt signal from the gpu. 13- clocks: device clocks (if applicable) 14 See ../clocks/clock-bindings.txt for details. 15- clock-names: the following clocks are required by a3xx, a4xx and a5xx 16 cores: 17 * "core" 18 * "iface" 19 * "mem_iface" 20 For GMU attached devices the GPU clocks are not used and are not required. The 21 following devices should not list clocks: 22 - qcom,adreno-630.2 23- iommus: optional phandle to an adreno iommu instance 24- operating-points-v2: optional phandle to the OPP operating points 25- interconnects: optional phandle to an interconnect provider. See 26 ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms 27 will have two paths; all others will have one path. 28- interconnect-names: The names of the interconnect paths that correspond to the 29 interconnects property. Values must be gfx-mem and ocmem. 30- qcom,gmu: For GMU attached devices a phandle to the GMU device that will 31 control the power for the GPU. Applicable targets: 32 - qcom,adreno-630.2 33- zap-shader: For a5xx and a6xx devices this node contains a memory-region that 34 points to reserved memory to store the zap shader that can be used to help 35 bring the GPU out of secure mode. 36- firmware-name: optional property of the 'zap-shader' node, listing the 37 relative path of the device specific zap firmware. 38- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and 39 a4xx Snapdragon SoCs. See 40 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. 41 42Optional properties: 43- #cooling-cells: The value must be 2. For details, please refer 44 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. 45 46Example 3xx/4xx: 47 48/ { 49 ... 50 51 gpu: adreno@fdb00000 { 52 compatible = "qcom,adreno-330.2", 53 "qcom,adreno"; 54 reg = <0xfdb00000 0x10000>; 55 reg-names = "kgsl_3d0_reg_memory"; 56 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-names = "kgsl_3d0_irq"; 58 clock-names = "core", 59 "iface", 60 "mem_iface"; 61 clocks = <&mmcc OXILI_GFX3D_CLK>, 62 <&mmcc OXILICX_AHB_CLK>, 63 <&mmcc OXILICX_AXI_CLK>; 64 sram = <&gpu_sram>; 65 power-domains = <&mmcc OXILICX_GDSC>; 66 operating-points-v2 = <&gpu_opp_table>; 67 iommus = <&gpu_iommu 0>; 68 #cooling-cells = <2>; 69 }; 70 71 gpu_sram: ocmem@fdd00000 { 72 compatible = "qcom,msm8974-ocmem"; 73 74 reg = <0xfdd00000 0x2000>, 75 <0xfec00000 0x180000>; 76 reg-names = "ctrl", 77 "mem"; 78 79 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 80 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 81 clock-names = "core", 82 "iface"; 83 84 #address-cells = <1>; 85 #size-cells = <1>; 86 87 gpu_sram: gpu-sram@0 { 88 reg = <0x0 0x100000>; 89 ranges = <0 0 0xfec00000 0x100000>; 90 }; 91 }; 92}; 93 94Example a6xx (with GMU): 95 96/ { 97 ... 98 99 gpu@5000000 { 100 compatible = "qcom,adreno-630.2", "qcom,adreno"; 101 #stream-id-cells = <16>; 102 103 reg = <0x5000000 0x40000>, <0x509e000 0x10>; 104 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 105 106 #cooling-cells = <2>; 107 108 /* 109 * Look ma, no clocks! The GPU clocks and power are 110 * controlled entirely by the GMU 111 */ 112 113 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 114 115 iommus = <&adreno_smmu 0>; 116 117 operating-points-v2 = <&gpu_opp_table>; 118 119 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; 120 interconnect-names = "gfx-mem"; 121 122 gpu_opp_table: opp-table { 123 compatible = "operating-points-v2"; 124 125 opp-430000000 { 126 opp-hz = /bits/ 64 <430000000>; 127 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 128 opp-peak-kBps = <5412000>; 129 }; 130 131 opp-355000000 { 132 opp-hz = /bits/ 64 <355000000>; 133 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 134 opp-peak-kBps = <3072000>; 135 }; 136 137 opp-267000000 { 138 opp-hz = /bits/ 64 <267000000>; 139 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 140 opp-peak-kBps = <3072000>; 141 }; 142 143 opp-180000000 { 144 opp-hz = /bits/ 64 <180000000>; 145 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 146 opp-peak-kBps = <1804000>; 147 }; 148 }; 149 150 qcom,gmu = <&gmu>; 151 152 zap-shader { 153 memory-region = <&zap_shader_region>; 154 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" 155 }; 156 }; 157}; 158