1# SPDX-License-Identifier: GPL-2.0-only 2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved 3%YAML 1.2 4--- 5 6$id: http://devicetree.org/schemas/display/msm/gmu.yaml# 7$schema: http://devicetree.org/meta-schemas/core.yaml# 8 9title: GMU attached to certain Adreno GPUs 10 11maintainers: 12 - Rob Clark <robdclark@gmail.com> 13 14description: | 15 These bindings describe the Graphics Management Unit (GMU) that is attached 16 to members of the Adreno A6xx GPU family. The GMU provides on-device power 17 management and support to improve power efficiency and reduce the load on 18 the CPU. 19 20properties: 21 compatible: 22 oneOf: 23 - items: 24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' 25 - const: qcom,adreno-gmu 26 - const: qcom,adreno-gmu-wrapper 27 28 reg: 29 minItems: 1 30 maxItems: 4 31 32 reg-names: 33 minItems: 1 34 maxItems: 4 35 36 clocks: 37 minItems: 4 38 maxItems: 7 39 40 clock-names: 41 minItems: 4 42 maxItems: 7 43 44 interrupts: 45 items: 46 - description: GMU HFI interrupt 47 - description: GMU interrupt 48 49 interrupt-names: 50 items: 51 - const: hfi 52 - const: gmu 53 54 power-domains: 55 items: 56 - description: CX power domain 57 - description: GX power domain 58 59 power-domain-names: 60 items: 61 - const: cx 62 - const: gx 63 64 iommus: 65 maxItems: 1 66 67 qcom,qmp: 68 $ref: /schemas/types.yaml#/definitions/phandle 69 description: Reference to the AOSS side-channel message RAM 70 71 operating-points-v2: true 72 73 opp-table: 74 type: object 75 76required: 77 - compatible 78 - reg 79 - reg-names 80 - power-domains 81 - power-domain-names 82 83additionalProperties: false 84 85allOf: 86 - if: 87 properties: 88 compatible: 89 contains: 90 enum: 91 - qcom,adreno-gmu-618.0 92 - qcom,adreno-gmu-630.2 93 then: 94 properties: 95 reg: 96 items: 97 - description: Core GMU registers 98 - description: GMU PDC registers 99 - description: GMU PDC sequence registers 100 reg-names: 101 items: 102 - const: gmu 103 - const: gmu_pdc 104 - const: gmu_pdc_seq 105 clocks: 106 items: 107 - description: GMU clock 108 - description: GPU CX clock 109 - description: GPU AXI clock 110 - description: GPU MEMNOC clock 111 clock-names: 112 items: 113 - const: gmu 114 - const: cxo 115 - const: axi 116 - const: memnoc 117 118 - if: 119 properties: 120 compatible: 121 contains: 122 enum: 123 - qcom,adreno-gmu-635.0 124 - qcom,adreno-gmu-660.1 125 then: 126 properties: 127 reg: 128 items: 129 - description: Core GMU registers 130 - description: Resource controller registers 131 - description: GMU PDC registers 132 reg-names: 133 items: 134 - const: gmu 135 - const: rscc 136 - const: gmu_pdc 137 clocks: 138 items: 139 - description: GMU clock 140 - description: GPU CX clock 141 - description: GPU AXI clock 142 - description: GPU MEMNOC clock 143 - description: GPU AHB clock 144 - description: GPU HUB CX clock 145 - description: GPU SMMU vote clock 146 clock-names: 147 items: 148 - const: gmu 149 - const: cxo 150 - const: axi 151 - const: memnoc 152 - const: ahb 153 - const: hub 154 - const: smmu_vote 155 156 - if: 157 properties: 158 compatible: 159 contains: 160 enum: 161 - qcom,adreno-gmu-640.1 162 then: 163 properties: 164 reg: 165 items: 166 - description: Core GMU registers 167 - description: GMU PDC registers 168 - description: GMU PDC sequence registers 169 reg-names: 170 items: 171 - const: gmu 172 - const: gmu_pdc 173 - const: gmu_pdc_seq 174 175 - if: 176 properties: 177 compatible: 178 contains: 179 enum: 180 - qcom,adreno-gmu-650.2 181 then: 182 properties: 183 reg: 184 items: 185 - description: Core GMU registers 186 - description: Resource controller registers 187 - description: GMU PDC registers 188 - description: GMU PDC sequence registers 189 reg-names: 190 items: 191 - const: gmu 192 - const: rscc 193 - const: gmu_pdc 194 - const: gmu_pdc_seq 195 196 - if: 197 properties: 198 compatible: 199 contains: 200 enum: 201 - qcom,adreno-gmu-640.1 202 - qcom,adreno-gmu-650.2 203 then: 204 properties: 205 clocks: 206 items: 207 - description: GPU AHB clock 208 - description: GMU clock 209 - description: GPU CX clock 210 - description: GPU AXI clock 211 - description: GPU MEMNOC clock 212 clock-names: 213 items: 214 - const: ahb 215 - const: gmu 216 - const: cxo 217 - const: axi 218 - const: memnoc 219 220 - if: 221 properties: 222 compatible: 223 contains: 224 enum: 225 - qcom,adreno-gmu-730.1 226 - qcom,adreno-gmu-740.1 227 then: 228 properties: 229 reg: 230 items: 231 - description: Core GMU registers 232 - description: Resource controller registers 233 - description: GMU PDC registers 234 reg-names: 235 items: 236 - const: gmu 237 - const: rscc 238 - const: gmu_pdc 239 clocks: 240 items: 241 - description: GPU AHB clock 242 - description: GMU clock 243 - description: GPU CX clock 244 - description: GPU AXI clock 245 - description: GPU MEMNOC clock 246 - description: GMU HUB clock 247 - description: GPUSS DEMET clock 248 clock-names: 249 items: 250 - const: ahb 251 - const: gmu 252 - const: cxo 253 - const: axi 254 - const: memnoc 255 - const: hub 256 - const: demet 257 258 required: 259 - qcom,qmp 260 261 - if: 262 properties: 263 compatible: 264 contains: 265 const: qcom,adreno-gmu-wrapper 266 then: 267 properties: 268 reg: 269 items: 270 - description: GMU wrapper register space 271 reg-names: 272 items: 273 - const: gmu 274 else: 275 required: 276 - clocks 277 - clock-names 278 - interrupts 279 - interrupt-names 280 - iommus 281 - operating-points-v2 282 283examples: 284 - | 285 #include <dt-bindings/clock/qcom,gpucc-sdm845.h> 286 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 287 #include <dt-bindings/interrupt-controller/irq.h> 288 #include <dt-bindings/interrupt-controller/arm-gic.h> 289 290 gmu: gmu@506a000 { 291 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 292 293 reg = <0x506a000 0x30000>, 294 <0xb280000 0x10000>, 295 <0xb480000 0x10000>; 296 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 297 298 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 299 <&gpucc GPU_CC_CXO_CLK>, 300 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 301 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 302 clock-names = "gmu", "cxo", "axi", "memnoc"; 303 304 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-names = "hfi", "gmu"; 307 308 power-domains = <&gpucc GPU_CX_GDSC>, 309 <&gpucc GPU_GX_GDSC>; 310 power-domain-names = "cx", "gx"; 311 312 iommus = <&adreno_smmu 5>; 313 operating-points-v2 = <&gmu_opp_table>; 314 }; 315 316 gmu_wrapper: gmu@596a000 { 317 compatible = "qcom,adreno-gmu-wrapper"; 318 reg = <0x0596a000 0x30000>; 319 reg-names = "gmu"; 320 power-domains = <&gpucc GPU_CX_GDSC>, 321 <&gpucc GPU_GX_GDSC>; 322 power-domain-names = "cx", "gx"; 323 }; 324