xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/gmu.yaml (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robdclark@gmail.com>
13
14description: |
15  These bindings describe the Graphics Management Unit (GMU) that is attached
16  to members of the Adreno A6xx GPU family. The GMU provides on-device power
17  management and support to improve power efficiency and reduce the load on
18  the CPU.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
25          - const: qcom,adreno-gmu
26      - const: qcom,adreno-gmu-wrapper
27
28  reg:
29    minItems: 1
30    maxItems: 4
31
32  reg-names:
33    minItems: 1
34    maxItems: 4
35
36  clocks:
37    minItems: 4
38    maxItems: 7
39
40  clock-names:
41    minItems: 4
42    maxItems: 7
43
44  interrupts:
45    items:
46      - description: GMU HFI interrupt
47      - description: GMU interrupt
48
49  interrupt-names:
50    items:
51      - const: hfi
52      - const: gmu
53
54  power-domains:
55    items:
56      - description: CX power domain
57      - description: GX power domain
58
59  power-domain-names:
60    items:
61      - const: cx
62      - const: gx
63
64  iommus:
65    maxItems: 1
66
67  operating-points-v2: true
68
69  opp-table:
70    type: object
71
72required:
73  - compatible
74  - reg
75  - reg-names
76  - power-domains
77  - power-domain-names
78
79additionalProperties: false
80
81allOf:
82  - if:
83      properties:
84        compatible:
85          contains:
86            enum:
87              - qcom,adreno-gmu-618.0
88              - qcom,adreno-gmu-630.2
89    then:
90      properties:
91        reg:
92          items:
93            - description: Core GMU registers
94            - description: GMU PDC registers
95            - description: GMU PDC sequence registers
96        reg-names:
97          items:
98            - const: gmu
99            - const: gmu_pdc
100            - const: gmu_pdc_seq
101        clocks:
102          items:
103            - description: GMU clock
104            - description: GPU CX clock
105            - description: GPU AXI clock
106            - description: GPU MEMNOC clock
107        clock-names:
108          items:
109            - const: gmu
110            - const: cxo
111            - const: axi
112            - const: memnoc
113
114  - if:
115      properties:
116        compatible:
117          contains:
118            enum:
119              - qcom,adreno-gmu-635.0
120              - qcom,adreno-gmu-660.1
121    then:
122      properties:
123        reg:
124          items:
125            - description: Core GMU registers
126            - description: Resource controller registers
127            - description: GMU PDC registers
128        reg-names:
129          items:
130            - const: gmu
131            - const: rscc
132            - const: gmu_pdc
133        clocks:
134          items:
135            - description: GMU clock
136            - description: GPU CX clock
137            - description: GPU AXI clock
138            - description: GPU MEMNOC clock
139            - description: GPU AHB clock
140            - description: GPU HUB CX clock
141            - description: GPU SMMU vote clock
142        clock-names:
143          items:
144            - const: gmu
145            - const: cxo
146            - const: axi
147            - const: memnoc
148            - const: ahb
149            - const: hub
150            - const: smmu_vote
151
152  - if:
153      properties:
154        compatible:
155          contains:
156            enum:
157              - qcom,adreno-gmu-640.1
158    then:
159      properties:
160        reg:
161          items:
162            - description: Core GMU registers
163            - description: GMU PDC registers
164            - description: GMU PDC sequence registers
165        reg-names:
166          items:
167            - const: gmu
168            - const: gmu_pdc
169            - const: gmu_pdc_seq
170
171  - if:
172      properties:
173        compatible:
174          contains:
175            enum:
176              - qcom,adreno-gmu-650.2
177    then:
178      properties:
179        reg:
180          items:
181            - description: Core GMU registers
182            - description: Resource controller registers
183            - description: GMU PDC registers
184            - description: GMU PDC sequence registers
185        reg-names:
186          items:
187            - const: gmu
188            - const: rscc
189            - const: gmu_pdc
190            - const: gmu_pdc_seq
191
192  - if:
193      properties:
194        compatible:
195          contains:
196            enum:
197              - qcom,adreno-gmu-640.1
198              - qcom,adreno-gmu-650.2
199    then:
200      properties:
201        clocks:
202          items:
203            - description: GPU AHB clock
204            - description: GMU clock
205            - description: GPU CX clock
206            - description: GPU AXI clock
207            - description: GPU MEMNOC clock
208        clock-names:
209          items:
210            - const: ahb
211            - const: gmu
212            - const: cxo
213            - const: axi
214            - const: memnoc
215
216  - if:
217      properties:
218        compatible:
219          contains:
220            const: qcom,adreno-gmu-wrapper
221    then:
222      properties:
223        reg:
224          items:
225            - description: GMU wrapper register space
226        reg-names:
227          items:
228            - const: gmu
229    else:
230      required:
231        - clocks
232        - clock-names
233        - interrupts
234        - interrupt-names
235        - iommus
236        - operating-points-v2
237
238examples:
239  - |
240    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
241    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
242    #include <dt-bindings/interrupt-controller/irq.h>
243    #include <dt-bindings/interrupt-controller/arm-gic.h>
244
245    gmu: gmu@506a000 {
246        compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
247
248        reg = <0x506a000 0x30000>,
249              <0xb280000 0x10000>,
250              <0xb480000 0x10000>;
251        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
252
253        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
254                 <&gpucc GPU_CC_CXO_CLK>,
255                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
256                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
257        clock-names = "gmu", "cxo", "axi", "memnoc";
258
259        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
260                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
261        interrupt-names = "hfi", "gmu";
262
263        power-domains = <&gpucc GPU_CX_GDSC>,
264                        <&gpucc GPU_GX_GDSC>;
265        power-domain-names = "cx", "gx";
266
267        iommus = <&adreno_smmu 5>;
268        operating-points-v2 = <&gmu_opp_table>;
269    };
270
271    gmu_wrapper: gmu@596a000 {
272        compatible = "qcom,adreno-gmu-wrapper";
273        reg = <0x0596a000 0x30000>;
274        reg-names = "gmu";
275        power-domains = <&gpucc GPU_CX_GDSC>,
276                        <&gpucc GPU_GX_GDSC>;
277        power-domain-names = "cx", "gx";
278    };
279