1Qualcomm Technologies Inc. adreno/snapdragon eDP output 2 3Required properties: 4- compatible: 5 * "qcom,mdss-edp" 6- reg: Physical base address and length of the registers of controller and PLL 7- reg-names: The names of register regions. The following regions are required: 8 * "edp" 9 * "pll_base" 10- interrupts: The interrupt signal from the eDP block. 11- power-domains: Should be <&mmcc MDSS_GDSC>. 12- clocks: device clocks 13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 14- clock-names: the following clocks are required: 15 * "core" 16 * "iface" 17 * "mdp_core" 18 * "pixel" 19 * "link" 20- #clock-cells: The value should be 1. 21- vdda-supply: phandle to vdda regulator device node 22- lvl-vdd-supply: phandle to regulator device node which is used to supply power 23 to HPD receiving chip 24- panel-en-gpios: GPIO pin to supply power to panel. 25- panel-hpd-gpios: GPIO pin used for eDP hpd. 26 27 28Example: 29 mdss_edp: qcom,mdss_edp@fd923400 { 30 compatible = "qcom,mdss-edp"; 31 reg-names = 32 "edp", 33 "pll_base"; 34 reg = <0xfd923400 0x700>, 35 <0xfd923a00 0xd4>; 36 interrupt-parent = <&mdss_mdp>; 37 interrupts = <12 0>; 38 power-domains = <&mmcc MDSS_GDSC>; 39 clock-names = 40 "core", 41 "pixel", 42 "iface", 43 "link", 44 "mdp_core"; 45 clocks = 46 <&mmcc MDSS_EDPAUX_CLK>, 47 <&mmcc MDSS_EDPPIXEL_CLK>, 48 <&mmcc MDSS_AHB_CLK>, 49 <&mmcc MDSS_EDPLINK_CLK>, 50 <&mmcc MDSS_MDP_CLK>; 51 #clock-cells = <1>; 52 vdda-supply = <&pma8084_l12>; 53 lvl-vdd-supply = <&lvl_vreg>; 54 panel-en-gpios = <&tlmm 137 0>; 55 panel-hpd-gpios = <&tlmm 103 0>; 56 }; 57