xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dsi-phy-28nm.yaml (revision fe75646a0234a261c0013bf1840fdac4acaf0cec) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 28nm PHY
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-28nm-hpm
19      - qcom,dsi-phy-28nm-hpm-fam-b
20      - qcom,dsi-phy-28nm-lp
21      - qcom,dsi-phy-28nm-8960
22
23  reg:
24    items:
25      - description: dsi pll register set
26      - description: dsi phy register set
27      - description: dsi phy regulator register set
28
29  reg-names:
30    items:
31      - const: dsi_pll
32      - const: dsi_phy
33      - const: dsi_phy_regulator
34
35  vddio-supply:
36    description: Phandle to vdd-io regulator device node.
37
38  qcom,dsi-phy-regulator-ldo-mode:
39    type: boolean
40    description: Indicates if the LDO mode PHY regulator is wanted.
41
42required:
43  - compatible
44  - reg
45  - reg-names
46  - vddio-supply
47
48unevaluatedProperties: false
49
50examples:
51  - |
52     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
53     #include <dt-bindings/clock/qcom,rpmh.h>
54
55     dsi-phy@fd922a00 {
56         compatible = "qcom,dsi-phy-28nm-lp";
57         reg = <0xfd922a00 0xd4>,
58               <0xfd922b00 0x2b0>,
59               <0xfd922d80 0x7b>;
60         reg-names = "dsi_pll",
61                     "dsi_phy",
62                     "dsi_phy_regulator";
63
64         #clock-cells = <1>;
65         #phy-cells = <0>;
66
67         vddio-supply = <&vddio_reg>;
68
69         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
70                  <&rpmhcc RPMH_CXO_CLK>;
71         clock-names = "iface", "ref";
72     };
73...
74