xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dsi-phy-28nm.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 28nm PHY
8
9maintainers:
10  - Krishna Manikandan <mkrishn@codeaurora.org>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-28nm-hpm
19      - qcom,dsi-phy-28nm-lp
20      - qcom,dsi-phy-28nm-8960
21
22  reg:
23    items:
24      - description: dsi pll register set
25      - description: dsi phy register set
26      - description: dsi phy regulator register set
27
28  reg-names:
29    items:
30      - const: dsi_pll
31      - const: dsi_phy
32      - const: dsi_phy_regulator
33
34  vddio-supply:
35    description: Phandle to vdd-io regulator device node.
36
37required:
38  - compatible
39  - reg
40  - reg-names
41  - vddio-supply
42
43unevaluatedProperties: false
44
45examples:
46  - |
47     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
48     #include <dt-bindings/clock/qcom,rpmh.h>
49
50     dsi-phy@fd922a00 {
51         compatible = "qcom,dsi-phy-28nm-lp";
52         reg = <0xfd922a00 0xd4>,
53               <0xfd922b00 0x2b0>,
54               <0xfd922d80 0x7b>;
55         reg-names = "dsi_pll",
56                     "dsi_phy",
57                     "dsi_phy_regulator";
58
59         #clock-cells = <1>;
60         #phy-cells = <0>;
61
62         vddio-supply = <&vddio_reg>;
63
64         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
65                  <&rpmhcc RPMH_CXO_CLK>;
66         clock-names = "iface", "ref";
67     };
68...
69