1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8916-dsi-ctrl 19 - qcom,msm8953-dsi-ctrl 20 - qcom,msm8974-dsi-ctrl 21 - qcom,msm8996-dsi-ctrl 22 - qcom,msm8998-dsi-ctrl 23 - qcom,qcm2290-dsi-ctrl 24 - qcom,sc7180-dsi-ctrl 25 - qcom,sc7280-dsi-ctrl 26 - qcom,sdm660-dsi-ctrl 27 - qcom,sdm845-dsi-ctrl 28 - qcom,sm6115-dsi-ctrl 29 - qcom,sm8150-dsi-ctrl 30 - qcom,sm8250-dsi-ctrl 31 - qcom,sm8350-dsi-ctrl 32 - qcom,sm8450-dsi-ctrl 33 - qcom,sm8550-dsi-ctrl 34 - const: qcom,mdss-dsi-ctrl 35 - enum: 36 - qcom,dsi-ctrl-6g-qcm2290 37 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 38 deprecated: true 39 40 reg: 41 maxItems: 1 42 43 reg-names: 44 const: dsi_ctrl 45 46 interrupts: 47 maxItems: 1 48 49 clocks: 50 description: | 51 Several clocks are used, depending on the variant. Typical ones are:: 52 - bus:: Display AHB clock. 53 - byte:: Display byte clock. 54 - byte_intf:: Display byte interface clock. 55 - core:: Display core clock. 56 - core_mss:: Core MultiMedia SubSystem clock. 57 - iface:: Display AXI clock. 58 - mdp_core:: MDP Core clock. 59 - mnoc:: MNOC clock 60 - pixel:: Display pixel clock. 61 minItems: 3 62 maxItems: 9 63 64 clock-names: 65 minItems: 3 66 maxItems: 9 67 68 phys: 69 maxItems: 1 70 71 phy-names: 72 deprecated: true 73 const: dsi 74 75 syscon-sfpb: 76 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 77 $ref: /schemas/types.yaml#/definitions/phandle 78 79 qcom,dual-dsi-mode: 80 type: boolean 81 description: | 82 Indicates if the DSI controller is driving a panel which needs 83 2 DSI links. 84 85 qcom,master-dsi: 86 type: boolean 87 description: | 88 Indicates if the DSI controller is the master DSI controller when 89 qcom,dual-dsi-mode enabled. 90 91 qcom,sync-dual-dsi: 92 type: boolean 93 description: | 94 Indicates if the DSI controller needs to sync the other DSI controller 95 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 96 97 assigned-clocks: 98 minItems: 2 99 maxItems: 4 100 description: | 101 Parents of "byte" and "pixel" for the given platform. 102 For DSIv2 platforms this should contain "byte", "esc", "src" and 103 "pixel_src" clocks. 104 105 assigned-clock-parents: 106 minItems: 2 107 maxItems: 4 108 description: | 109 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 110 111 power-domains: 112 maxItems: 1 113 114 operating-points-v2: true 115 116 opp-table: 117 type: object 118 119 ports: 120 $ref: /schemas/graph.yaml#/properties/ports 121 description: | 122 Contains DSI controller input and output ports as children, each 123 containing one endpoint subnode. 124 125 properties: 126 port@0: 127 $ref: /schemas/graph.yaml#/$defs/port-base 128 unevaluatedProperties: false 129 description: | 130 Input endpoints of the controller. 131 properties: 132 endpoint: 133 $ref: /schemas/media/video-interfaces.yaml# 134 unevaluatedProperties: false 135 properties: 136 data-lanes: 137 maxItems: 4 138 minItems: 1 139 items: 140 enum: [ 0, 1, 2, 3 ] 141 142 port@1: 143 $ref: /schemas/graph.yaml#/$defs/port-base 144 unevaluatedProperties: false 145 description: | 146 Output endpoints of the controller. 147 properties: 148 endpoint: 149 $ref: /schemas/media/video-interfaces.yaml# 150 unevaluatedProperties: false 151 properties: 152 data-lanes: 153 maxItems: 4 154 minItems: 1 155 items: 156 enum: [ 0, 1, 2, 3 ] 157 158 required: 159 - port@0 160 - port@1 161 162 avdd-supply: 163 description: 164 Phandle to vdd regulator device node 165 166 vcca-supply: 167 description: 168 Phandle to vdd regulator device node 169 170 vdd-supply: 171 description: 172 VDD regulator 173 174 vddio-supply: 175 description: 176 VDD-IO regulator 177 178 vdda-supply: 179 description: 180 VDDA regulator 181 182required: 183 - compatible 184 - reg 185 - reg-names 186 - interrupts 187 - clocks 188 - clock-names 189 - phys 190 - assigned-clocks 191 - assigned-clock-parents 192 - ports 193 194allOf: 195 - $ref: ../dsi-controller.yaml# 196 - if: 197 properties: 198 compatible: 199 contains: 200 enum: 201 - qcom,apq8064-dsi-ctrl 202 then: 203 properties: 204 clocks: 205 maxItems: 7 206 clock-names: 207 items: 208 - const: iface 209 - const: bus 210 - const: core_mmss 211 - const: src 212 - const: byte 213 - const: pixel 214 - const: core 215 216 - if: 217 properties: 218 compatible: 219 contains: 220 enum: 221 - qcom,msm8916-dsi-ctrl 222 then: 223 properties: 224 clocks: 225 maxItems: 6 226 clock-names: 227 items: 228 - const: mdp_core 229 - const: iface 230 - const: bus 231 - const: byte 232 - const: pixel 233 - const: core 234 235 - if: 236 properties: 237 compatible: 238 contains: 239 enum: 240 - qcom,msm8953-dsi-ctrl 241 then: 242 properties: 243 clocks: 244 maxItems: 6 245 clock-names: 246 items: 247 - const: mdp_core 248 - const: iface 249 - const: bus 250 - const: byte 251 - const: pixel 252 - const: core 253 254 - if: 255 properties: 256 compatible: 257 contains: 258 enum: 259 - qcom,msm8974-dsi-ctrl 260 then: 261 properties: 262 clocks: 263 maxItems: 7 264 clock-names: 265 items: 266 - const: mdp_core 267 - const: iface 268 - const: bus 269 - const: byte 270 - const: pixel 271 - const: core 272 - const: core_mmss 273 274 - if: 275 properties: 276 compatible: 277 contains: 278 enum: 279 - qcom,msm8996-dsi-ctrl 280 then: 281 properties: 282 clocks: 283 maxItems: 7 284 clock-names: 285 items: 286 - const: mdp_core 287 - const: byte 288 - const: iface 289 - const: bus 290 - const: core_mmss 291 - const: pixel 292 - const: core 293 294 - if: 295 properties: 296 compatible: 297 contains: 298 enum: 299 - qcom,msm8998-dsi-ctrl 300 then: 301 properties: 302 clocks: 303 maxItems: 6 304 clock-names: 305 items: 306 - const: byte 307 - const: byte_intf 308 - const: pixel 309 - const: core 310 - const: iface 311 - const: bus 312 313 - if: 314 properties: 315 compatible: 316 contains: 317 enum: 318 - qcom,sc7180-dsi-ctrl 319 - qcom,sc7280-dsi-ctrl 320 - qcom,sm8150-dsi-ctrl 321 - qcom,sm8250-dsi-ctrl 322 - qcom,sm8350-dsi-ctrl 323 - qcom,sm8450-dsi-ctrl 324 - qcom,sm8550-dsi-ctrl 325 then: 326 properties: 327 clocks: 328 maxItems: 6 329 clock-names: 330 items: 331 - const: byte 332 - const: byte_intf 333 - const: pixel 334 - const: core 335 - const: iface 336 - const: bus 337 338 - if: 339 properties: 340 compatible: 341 contains: 342 enum: 343 - qcom,sdm660-dsi-ctrl 344 then: 345 properties: 346 clocks: 347 maxItems: 9 348 clock-names: 349 items: 350 - const: mdp_core 351 - const: byte 352 - const: byte_intf 353 - const: mnoc 354 - const: iface 355 - const: bus 356 - const: core_mmss 357 - const: pixel 358 - const: core 359 360 - if: 361 properties: 362 compatible: 363 contains: 364 enum: 365 - qcom,sdm845-dsi-ctrl 366 - qcom,sm6115-dsi-ctrl 367 then: 368 properties: 369 clocks: 370 maxItems: 6 371 clock-names: 372 items: 373 - const: byte 374 - const: byte_intf 375 - const: pixel 376 - const: core 377 - const: iface 378 - const: bus 379 380unevaluatedProperties: false 381 382examples: 383 - | 384 #include <dt-bindings/interrupt-controller/arm-gic.h> 385 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 386 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 387 #include <dt-bindings/power/qcom-rpmpd.h> 388 389 dsi@ae94000 { 390 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 391 reg = <0x0ae94000 0x400>; 392 reg-names = "dsi_ctrl"; 393 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 interrupt-parent = <&mdss>; 398 interrupts = <4>; 399 400 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 401 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 402 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 403 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 404 <&dispcc DISP_CC_MDSS_AHB_CLK>, 405 <&dispcc DISP_CC_MDSS_AXI_CLK>; 406 clock-names = "byte", 407 "byte_intf", 408 "pixel", 409 "core", 410 "iface", 411 "bus"; 412 413 phys = <&dsi0_phy>; 414 phy-names = "dsi"; 415 416 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 417 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 418 419 power-domains = <&rpmhpd SC7180_CX>; 420 operating-points-v2 = <&dsi_opp_table>; 421 422 ports { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 426 port@0 { 427 reg = <0>; 428 dsi0_in: endpoint { 429 remote-endpoint = <&dpu_intf1_out>; 430 }; 431 }; 432 433 port@1 { 434 reg = <1>; 435 dsi0_out: endpoint { 436 remote-endpoint = <&sn65dsi86_in>; 437 data-lanes = <0 1 2 3>; 438 }; 439 }; 440 }; 441 }; 442... 443