1Qualcomm Technologies, Inc. DPU KMS 2 3Description: 4 5Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 6sub-blocks like DPU display controller, DSI and DP interfaces etc. 7The DPU display controller is found in SDM845 SoC. 8 9MDSS: 10Required properties: 11- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" 12- reg: physical base address and length of controller's registers. 13- reg-names: register region names. The following region is required: 14 * "mdss" 15- power-domains: a power domain consumer specifier according to 16 Documentation/devicetree/bindings/power/power_domain.txt 17- clocks: list of clock specifiers for clocks needed by the device. 18- clock-names: device clock names, must be in same order as clocks property. 19 The following clocks are required: 20 * "iface" 21 * "bus" 22 * "core" 23- interrupts: interrupt signal from MDSS. 24- interrupt-controller: identifies the node as an interrupt controller. 25- #interrupt-cells: specifies the number of cells needed to encode an interrupt 26 source, should be 1. 27- iommus: phandle of iommu device node. 28- #address-cells: number of address cells for the MDSS children. Should be 1. 29- #size-cells: Should be 1. 30- ranges: parent bus address space is the same as the child bus address space. 31- interconnects : interconnect path specifier for MDSS according to 32 Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be 33 2 paths corresponding to 2 AXI ports. 34- interconnect-names : MDSS will have 2 port names to differentiate between the 35 2 interconnect paths defined with interconnect specifier. 36 37Optional properties: 38- assigned-clocks: list of clock specifiers for clocks needing rate assignment 39- assigned-clock-rates: list of clock frequencies sorted in the same order as 40 the assigned-clocks property. 41 42MDP: 43Required properties: 44- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" 45- reg: physical base address and length of controller's registers. 46- reg-names : register region names. The following region is required: 47 * "mdp" 48 * "vbif" 49- clocks: list of clock specifiers for clocks needed by the device. 50- clock-names: device clock names, must be in same order as clocks property. 51 The following clocks are required. 52 * "bus" 53 * "iface" 54 * "core" 55 * "vsync" 56- interrupts: interrupt line from DPU to MDSS. 57- ports: contains the list of output ports from DPU device. These ports connect 58 to interfaces that are external to the DPU hardware, such as DSI, DP etc. 59 60 Each output port contains an endpoint that describes how it is connected to an 61 external interface. These are described by the standard properties documented 62 here: 63 Documentation/devicetree/bindings/graph.txt 64 Documentation/devicetree/bindings/media/video-interfaces.txt 65 66 Port 0 -> DPU_INTF1 (DSI1) 67 Port 1 -> DPU_INTF2 (DSI2) 68 69Optional properties: 70- assigned-clocks: list of clock specifiers for clocks needing rate assignment 71- assigned-clock-rates: list of clock frequencies sorted in the same order as 72 the assigned-clocks property. 73 74Example: 75 76 mdss: mdss@ae00000 { 77 compatible = "qcom,sdm845-mdss"; 78 reg = <0xae00000 0x1000>; 79 reg-names = "mdss"; 80 81 power-domains = <&clock_dispcc 0>; 82 83 clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, 84 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; 85 clock-names = "iface", "bus", "core"; 86 87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; 88 assigned-clock-rates = <300000000>; 89 90 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-controller; 92 #interrupt-cells = <1>; 93 94 interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>, 95 <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>; 96 97 interconnect-names = "mdp0-mem", "mdp1-mem"; 98 99 iommus = <&apps_iommu 0>; 100 101 #address-cells = <2>; 102 #size-cells = <1>; 103 ranges = <0 0 0xae00000 0xb2008>; 104 105 mdss_mdp: mdp@ae01000 { 106 compatible = "qcom,sdm845-dpu"; 107 reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; 108 reg-names = "mdp", "vbif"; 109 110 clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, 111 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, 112 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, 113 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; 114 clock-names = "iface", "bus", "core", "vsync"; 115 116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, 117 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; 118 assigned-clock-rates = <0 0 300000000 19200000>; 119 120 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 121 122 ports { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 126 port@0 { 127 reg = <0>; 128 dpu_intf1_out: endpoint { 129 remote-endpoint = <&dsi0_in>; 130 }; 131 }; 132 133 port@1 { 134 reg = <1>; 135 dpu_intf2_out: endpoint { 136 remote-endpoint = <&dsi1_in>; 137 }; 138 }; 139 }; 140 }; 141 }; 142