xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dpu-sdm845.yaml (revision c7046f76c2c027b00c0e6ba57cfd28f1a78f5e23) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU dt properties for SDM845 target
8
9maintainers:
10  - Krishna Manikandan <mkrishn@codeaurora.org>
11
12description: |
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS and DPU are mentioned for SDM845 target.
16
17properties:
18  compatible:
19    items:
20      - const: qcom,sdm845-mdss
21
22  reg:
23    maxItems: 1
24
25  reg-names:
26    const: mdss
27
28  power-domains:
29    maxItems: 1
30
31  clocks:
32    items:
33      - description: Display AHB clock from gcc
34      - description: Display core clock
35
36  clock-names:
37    items:
38      - const: iface
39      - const: core
40
41  interrupts:
42    maxItems: 1
43
44  interrupt-controller: true
45
46  "#address-cells": true
47
48  "#size-cells": true
49
50  "#interrupt-cells":
51    const: 1
52
53  iommus:
54    items:
55      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
56      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
57
58  ranges: true
59
60patternProperties:
61  "^display-controller@[0-9a-f]+$":
62    type: object
63    description: Node containing the properties of DPU.
64
65    properties:
66      compatible:
67        items:
68          - const: qcom,sdm845-dpu
69
70      reg:
71        items:
72          - description: Address offset and size for mdp register set
73          - description: Address offset and size for vbif register set
74
75      reg-names:
76        items:
77          - const: mdp
78          - const: vbif
79
80      clocks:
81        items:
82          - description: Display ahb clock
83          - description: Display axi clock
84          - description: Display core clock
85          - description: Display vsync clock
86
87      clock-names:
88        items:
89          - const: iface
90          - const: bus
91          - const: core
92          - const: vsync
93
94      interrupts:
95        maxItems: 1
96
97      power-domains:
98        maxItems: 1
99
100      operating-points-v2: true
101      ports:
102        $ref: /schemas/graph.yaml#/properties/ports
103        description: |
104          Contains the list of output ports from DPU device. These ports
105          connect to interfaces that are external to the DPU hardware,
106          such as DSI, DP etc. Each output port contains an endpoint that
107          describes how it is connected to an external interface.
108
109        properties:
110          port@0:
111            $ref: /schemas/graph.yaml#/properties/port
112            description: DPU_INTF1 (DSI1)
113
114          port@1:
115            $ref: /schemas/graph.yaml#/properties/port
116            description: DPU_INTF2 (DSI2)
117
118        required:
119          - port@0
120          - port@1
121
122    required:
123      - compatible
124      - reg
125      - reg-names
126      - clocks
127      - interrupts
128      - power-domains
129      - operating-points-v2
130      - ports
131
132required:
133  - compatible
134  - reg
135  - reg-names
136  - power-domains
137  - clocks
138  - interrupts
139  - interrupt-controller
140  - iommus
141  - ranges
142
143additionalProperties: false
144
145examples:
146  - |
147    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
148    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
149    #include <dt-bindings/interrupt-controller/arm-gic.h>
150    #include <dt-bindings/power/qcom-rpmpd.h>
151
152    display-subsystem@ae00000 {
153          #address-cells = <1>;
154          #size-cells = <1>;
155          compatible = "qcom,sdm845-mdss";
156          reg = <0x0ae00000 0x1000>;
157          reg-names = "mdss";
158          power-domains = <&dispcc MDSS_GDSC>;
159
160          clocks = <&gcc GCC_DISP_AHB_CLK>,
161                   <&dispcc DISP_CC_MDSS_MDP_CLK>;
162          clock-names = "iface", "core";
163
164          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
165          interrupt-controller;
166          #interrupt-cells = <1>;
167
168          iommus = <&apps_smmu 0x880 0x8>,
169                   <&apps_smmu 0xc80 0x8>;
170          ranges;
171
172          display-controller@ae01000 {
173                    compatible = "qcom,sdm845-dpu";
174                    reg = <0x0ae01000 0x8f000>,
175                          <0x0aeb0000 0x2008>;
176                    reg-names = "mdp", "vbif";
177
178                    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
179                             <&dispcc DISP_CC_MDSS_AXI_CLK>,
180                             <&dispcc DISP_CC_MDSS_MDP_CLK>,
181                             <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
182                    clock-names = "iface", "bus", "core", "vsync";
183
184                    interrupt-parent = <&mdss>;
185                    interrupts = <0>;
186                    power-domains = <&rpmhpd SDM845_CX>;
187                    operating-points-v2 = <&mdp_opp_table>;
188
189                    ports {
190                           #address-cells = <1>;
191                           #size-cells = <0>;
192
193                           port@0 {
194                                   reg = <0>;
195                                   dpu_intf1_out: endpoint {
196                                                  remote-endpoint = <&dsi0_in>;
197                                   };
198                           };
199
200                           port@1 {
201                                   reg = <1>;
202                                   dpu_intf2_out: endpoint {
203                                                  remote-endpoint = <&dsi1_in>;
204                                   };
205                           };
206                    };
207          };
208    };
209...
210