xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dpu-sc7280.yaml (revision f81cdf24ba5436367377f7c8e8f51f6df2a75ca7) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU dt properties for SC7280
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description: |
13  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS and DPU are mentioned for SC7280.
16
17properties:
18  compatible:
19    const: qcom,sc7280-mdss
20
21  reg:
22    maxItems: 1
23
24  reg-names:
25    const: mdss
26
27  power-domains:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Display AHB clock from gcc
33      - description: Display AHB clock from dispcc
34      - description: Display core clock
35
36  clock-names:
37    items:
38      - const: iface
39      - const: ahb
40      - const: core
41
42  interrupts:
43    maxItems: 1
44
45  interrupt-controller: true
46
47  "#address-cells": true
48
49  "#size-cells": true
50
51  "#interrupt-cells":
52    const: 1
53
54  iommus:
55    items:
56      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
57
58  ranges: true
59
60  interconnects:
61    items:
62      - description: Interconnect path specifying the port ids for data bus
63
64  interconnect-names:
65    const: mdp0-mem
66
67  resets:
68    items:
69      - description: MDSS_CORE reset
70
71patternProperties:
72  "^display-controller@[0-9a-f]+$":
73    type: object
74    description: Node containing the properties of DPU.
75    additionalProperties: false
76
77    properties:
78      compatible:
79        const: qcom,sc7280-dpu
80
81      reg:
82        items:
83          - description: Address offset and size for mdp register set
84          - description: Address offset and size for vbif register set
85
86      reg-names:
87        items:
88          - const: mdp
89          - const: vbif
90
91      clocks:
92        items:
93          - description: Display hf axi clock
94          - description: Display sf axi clock
95          - description: Display ahb clock
96          - description: Display lut clock
97          - description: Display core clock
98          - description: Display vsync clock
99
100      clock-names:
101        items:
102          - const: bus
103          - const: nrt_bus
104          - const: iface
105          - const: lut
106          - const: core
107          - const: vsync
108
109      interrupts:
110        maxItems: 1
111
112      power-domains:
113        maxItems: 1
114
115      operating-points-v2: true
116      opp-table:
117        type: object
118
119      ports:
120        $ref: /schemas/graph.yaml#/properties/ports
121        description: |
122          Contains the list of output ports from DPU device. These ports
123          connect to interfaces that are external to the DPU hardware,
124          such as DSI, DP etc. Each output port contains an endpoint that
125          describes how it is connected to an external interface.
126
127        properties:
128          port@0:
129            $ref: /schemas/graph.yaml#/properties/port
130            description: DPU_INTF1 (DSI)
131
132          port@1:
133            $ref: /schemas/graph.yaml#/properties/port
134            description: DPU_INTF5 (EDP)
135
136        required:
137          - port@0
138
139    required:
140      - compatible
141      - reg
142      - reg-names
143      - clocks
144      - interrupts
145      - power-domains
146      - operating-points-v2
147      - ports
148
149required:
150  - compatible
151  - reg
152  - reg-names
153  - power-domains
154  - clocks
155  - interrupts
156  - interrupt-controller
157  - iommus
158  - ranges
159
160additionalProperties: false
161
162examples:
163  - |
164    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
165    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
166    #include <dt-bindings/interrupt-controller/arm-gic.h>
167    #include <dt-bindings/interconnect/qcom,sc7280.h>
168    #include <dt-bindings/power/qcom-rpmpd.h>
169
170    display-subsystem@ae00000 {
171         #address-cells = <1>;
172         #size-cells = <1>;
173         compatible = "qcom,sc7280-mdss";
174         reg = <0xae00000 0x1000>;
175         reg-names = "mdss";
176         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
177         clocks = <&gcc GCC_DISP_AHB_CLK>,
178                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
179                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
180         clock-names = "iface",
181                       "ahb",
182                       "core";
183
184         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
185         interrupt-controller;
186         #interrupt-cells = <1>;
187
188         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
189         interconnect-names = "mdp0-mem";
190
191         iommus = <&apps_smmu 0x900 0x402>;
192         ranges;
193
194         display-controller@ae01000 {
195                   compatible = "qcom,sc7280-dpu";
196                   reg = <0x0ae01000 0x8f000>,
197                         <0x0aeb0000 0x2008>;
198
199                   reg-names = "mdp", "vbif";
200
201                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
202                            <&gcc GCC_DISP_SF_AXI_CLK>,
203                            <&dispcc DISP_CC_MDSS_AHB_CLK>,
204                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
205                            <&dispcc DISP_CC_MDSS_MDP_CLK>,
206                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
207                   clock-names = "bus",
208                                 "nrt_bus",
209                                 "iface",
210                                 "lut",
211                                 "core",
212                                 "vsync";
213
214                   interrupt-parent = <&mdss>;
215                   interrupts = <0>;
216                   power-domains = <&rpmhpd SC7280_CX>;
217                   operating-points-v2 = <&mdp_opp_table>;
218
219                   ports {
220                           #address-cells = <1>;
221                           #size-cells = <0>;
222
223                           port@0 {
224                                   reg = <0>;
225                                   dpu_intf1_out: endpoint {
226                                           remote-endpoint = <&dsi0_in>;
227                                   };
228                           };
229
230                           port@1 {
231                                   reg = <1>;
232                                   dpu_intf5_out: endpoint {
233                                           remote-endpoint = <&edp_in>;
234                                   };
235                           };
236                   };
237         };
238    };
239...
240