xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dpu-sc7280.yaml (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU dt properties for SC7280
8
9maintainers:
10  - Krishna Manikandan <mkrishn@codeaurora.org>
11
12description: |
13  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS and DPU are mentioned for SC7280.
16
17properties:
18  compatible:
19    const: qcom,sc7280-mdss
20
21  reg:
22    maxItems: 1
23
24  reg-names:
25    const: mdss
26
27  power-domains:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Display AHB clock from gcc
33      - description: Display AHB clock from dispcc
34      - description: Display core clock
35
36  clock-names:
37    items:
38      - const: iface
39      - const: ahb
40      - const: core
41
42  interrupts:
43    maxItems: 1
44
45  interrupt-controller: true
46
47  "#address-cells": true
48
49  "#size-cells": true
50
51  "#interrupt-cells":
52    const: 1
53
54  iommus:
55    items:
56      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
57
58  ranges: true
59
60  interconnects:
61    items:
62      - description: Interconnect path specifying the port ids for data bus
63
64  interconnect-names:
65    const: mdp0-mem
66
67patternProperties:
68  "^display-controller@[0-9a-f]+$":
69    type: object
70    description: Node containing the properties of DPU.
71
72    properties:
73      compatible:
74        const: qcom,sc7280-dpu
75
76      reg:
77        items:
78          - description: Address offset and size for mdp register set
79          - description: Address offset and size for vbif register set
80
81      reg-names:
82        items:
83          - const: mdp
84          - const: vbif
85
86      clocks:
87        items:
88          - description: Display hf axi clock
89          - description: Display sf axi clock
90          - description: Display ahb clock
91          - description: Display lut clock
92          - description: Display core clock
93          - description: Display vsync clock
94
95      clock-names:
96        items:
97          - const: bus
98          - const: nrt_bus
99          - const: iface
100          - const: lut
101          - const: core
102          - const: vsync
103
104      interrupts:
105        maxItems: 1
106
107      power-domains:
108        maxItems: 1
109
110      operating-points-v2: true
111
112      ports:
113        $ref: /schemas/graph.yaml#/properties/ports
114        description: |
115          Contains the list of output ports from DPU device. These ports
116          connect to interfaces that are external to the DPU hardware,
117          such as DSI, DP etc. Each output port contains an endpoint that
118          describes how it is connected to an external interface.
119
120        properties:
121          port@0:
122            $ref: /schemas/graph.yaml#/properties/port
123            description: DPU_INTF1 (DSI)
124
125          port@1:
126            $ref: /schemas/graph.yaml#/properties/port
127            description: DPU_INTF5 (EDP)
128
129        required:
130          - port@0
131
132    required:
133      - compatible
134      - reg
135      - reg-names
136      - clocks
137      - interrupts
138      - power-domains
139      - operating-points-v2
140      - ports
141
142required:
143  - compatible
144  - reg
145  - reg-names
146  - power-domains
147  - clocks
148  - interrupts
149  - interrupt-controller
150  - iommus
151  - ranges
152
153additionalProperties: false
154
155examples:
156  - |
157    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
158    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
159    #include <dt-bindings/interrupt-controller/arm-gic.h>
160    #include <dt-bindings/interconnect/qcom,sc7280.h>
161    #include <dt-bindings/power/qcom-rpmpd.h>
162
163    display-subsystem@ae00000 {
164         #address-cells = <1>;
165         #size-cells = <1>;
166         compatible = "qcom,sc7280-mdss";
167         reg = <0xae00000 0x1000>;
168         reg-names = "mdss";
169         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
170         clocks = <&gcc GCC_DISP_AHB_CLK>,
171                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
172                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
173         clock-names = "iface",
174                       "ahb",
175                       "core";
176
177         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
178         interrupt-controller;
179         #interrupt-cells = <1>;
180
181         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
182         interconnect-names = "mdp0-mem";
183
184         iommus = <&apps_smmu 0x900 0x402>;
185         ranges;
186
187         display-controller@ae01000 {
188                   compatible = "qcom,sc7280-dpu";
189                   reg = <0x0ae01000 0x8f000>,
190                         <0x0aeb0000 0x2008>;
191
192                   reg-names = "mdp", "vbif";
193
194                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
195                            <&gcc GCC_DISP_SF_AXI_CLK>,
196                            <&dispcc DISP_CC_MDSS_AHB_CLK>,
197                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
198                            <&dispcc DISP_CC_MDSS_MDP_CLK>,
199                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
200                   clock-names = "bus",
201                                 "nrt_bus",
202                                 "iface",
203                                 "lut",
204                                 "core",
205                                 "vsync";
206
207                   interrupt-parent = <&mdss>;
208                   interrupts = <0>;
209                   power-domains = <&rpmhpd SC7280_CX>;
210                   operating-points-v2 = <&mdp_opp_table>;
211
212                   ports {
213                           #address-cells = <1>;
214                           #size-cells = <0>;
215
216                           port@0 {
217                                   reg = <0>;
218                                   dpu_intf1_out: endpoint {
219                                           remote-endpoint = <&dsi0_in>;
220                                   };
221                           };
222
223                           port@1 {
224                                   reg = <1>;
225                                   dpu_intf5_out: endpoint {
226                                           remote-endpoint = <&edp_in>;
227                                   };
228                           };
229                   };
230         };
231    };
232...
233