xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dpu-sc7180.yaml (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU dt properties for SC7180 target
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description: |
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS and DPU are mentioned for SC7180 target.
16
17properties:
18  compatible:
19    items:
20      - const: qcom,sc7180-mdss
21
22  reg:
23    maxItems: 1
24
25  reg-names:
26    const: mdss
27
28  power-domains:
29    maxItems: 1
30
31  clocks:
32    items:
33      - description: Display AHB clock from gcc
34      - description: Display AHB clock from dispcc
35      - description: Display core clock
36
37  clock-names:
38    items:
39      - const: iface
40      - const: ahb
41      - const: core
42
43  interrupts:
44    maxItems: 1
45
46  interrupt-controller: true
47
48  "#address-cells": true
49
50  "#size-cells": true
51
52  "#interrupt-cells":
53    const: 1
54
55  iommus:
56    items:
57      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58
59  ranges: true
60
61  interconnects:
62    items:
63      - description: Interconnect path specifying the port ids for data bus
64
65  interconnect-names:
66    const: mdp0-mem
67
68  resets:
69    items:
70      - description: MDSS_CORE reset
71
72patternProperties:
73  "^display-controller@[0-9a-f]+$":
74    type: object
75    description: Node containing the properties of DPU.
76
77    properties:
78      compatible:
79        items:
80          - const: qcom,sc7180-dpu
81
82      reg:
83        items:
84          - description: Address offset and size for mdp register set
85          - description: Address offset and size for vbif register set
86
87      reg-names:
88        items:
89          - const: mdp
90          - const: vbif
91
92      clocks:
93        items:
94          - description: Display hf axi clock
95          - description: Display ahb clock
96          - description: Display rotator clock
97          - description: Display lut clock
98          - description: Display core clock
99          - description: Display vsync clock
100
101      clock-names:
102        items:
103          - const: bus
104          - const: iface
105          - const: rot
106          - const: lut
107          - const: core
108          - const: vsync
109
110      interrupts:
111        maxItems: 1
112
113      power-domains:
114        maxItems: 1
115
116      operating-points-v2: true
117
118      ports:
119        $ref: /schemas/graph.yaml#/properties/ports
120        description: |
121          Contains the list of output ports from DPU device. These ports
122          connect to interfaces that are external to the DPU hardware,
123          such as DSI, DP etc. Each output port contains an endpoint that
124          describes how it is connected to an external interface.
125
126        properties:
127          port@0:
128            $ref: /schemas/graph.yaml#/properties/port
129            description: DPU_INTF1 (DSI1)
130
131          port@2:
132            $ref: /schemas/graph.yaml#/properties/port
133            description: DPU_INTF0 (DP)
134
135        required:
136          - port@0
137
138    required:
139      - compatible
140      - reg
141      - reg-names
142      - clocks
143      - interrupts
144      - power-domains
145      - operating-points-v2
146      - ports
147
148required:
149  - compatible
150  - reg
151  - reg-names
152  - power-domains
153  - clocks
154  - interrupts
155  - interrupt-controller
156  - iommus
157  - ranges
158
159additionalProperties: false
160
161examples:
162  - |
163    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
164    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
165    #include <dt-bindings/interrupt-controller/arm-gic.h>
166    #include <dt-bindings/interconnect/qcom,sdm845.h>
167    #include <dt-bindings/power/qcom-rpmpd.h>
168
169    display-subsystem@ae00000 {
170         #address-cells = <1>;
171         #size-cells = <1>;
172         compatible = "qcom,sc7180-mdss";
173         reg = <0xae00000 0x1000>;
174         reg-names = "mdss";
175         power-domains = <&dispcc MDSS_GDSC>;
176         clocks = <&gcc GCC_DISP_AHB_CLK>,
177                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
178                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
179         clock-names = "iface", "ahb", "core";
180
181         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
182         interrupt-controller;
183         #interrupt-cells = <1>;
184
185         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
186         interconnect-names = "mdp0-mem";
187
188         iommus = <&apps_smmu 0x800 0x2>;
189         ranges;
190
191         display-controller@ae01000 {
192                   compatible = "qcom,sc7180-dpu";
193                   reg = <0x0ae01000 0x8f000>,
194                         <0x0aeb0000 0x2008>;
195
196                   reg-names = "mdp", "vbif";
197
198                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
199                            <&dispcc DISP_CC_MDSS_AHB_CLK>,
200                            <&dispcc DISP_CC_MDSS_ROT_CLK>,
201                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
202                            <&dispcc DISP_CC_MDSS_MDP_CLK>,
203                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
204                   clock-names = "bus", "iface", "rot", "lut", "core",
205                                 "vsync";
206
207                   interrupt-parent = <&mdss>;
208                   interrupts = <0>;
209                   power-domains = <&rpmhpd SC7180_CX>;
210                   operating-points-v2 = <&mdp_opp_table>;
211
212                   ports {
213                           #address-cells = <1>;
214                           #size-cells = <0>;
215
216                           port@0 {
217                                   reg = <0>;
218                                   dpu_intf1_out: endpoint {
219                                                  remote-endpoint = <&dsi0_in>;
220                                   };
221                           };
222
223                            port@2 {
224                                    reg = <2>;
225                                    dpu_intf0_out: endpoint {
226                                                   remote-endpoint = <&dp_in>;
227                                    };
228                            };
229                   };
230         };
231    };
232...
233