xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dpu-sc7180.yaml (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU dt properties for SC7180 target
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description: |
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS and DPU are mentioned for SC7180 target.
16
17properties:
18  compatible:
19    items:
20      - const: qcom,sc7180-mdss
21
22  reg:
23    maxItems: 1
24
25  reg-names:
26    const: mdss
27
28  power-domains:
29    maxItems: 1
30
31  clocks:
32    items:
33      - description: Display AHB clock from gcc
34      - description: Display AHB clock from dispcc
35      - description: Display core clock
36
37  clock-names:
38    items:
39      - const: iface
40      - const: ahb
41      - const: core
42
43  interrupts:
44    maxItems: 1
45
46  interrupt-controller: true
47
48  "#address-cells": true
49
50  "#size-cells": true
51
52  "#interrupt-cells":
53    const: 1
54
55  iommus:
56    items:
57      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58
59  ranges: true
60
61  interconnects:
62    items:
63      - description: Interconnect path specifying the port ids for data bus
64
65  interconnect-names:
66    const: mdp0-mem
67
68  resets:
69    items:
70      - description: MDSS_CORE reset
71
72patternProperties:
73  "^display-controller@[0-9a-f]+$":
74    type: object
75    description: Node containing the properties of DPU.
76    additionalProperties: false
77
78    properties:
79      compatible:
80        items:
81          - const: qcom,sc7180-dpu
82
83      reg:
84        items:
85          - description: Address offset and size for mdp register set
86          - description: Address offset and size for vbif register set
87
88      reg-names:
89        items:
90          - const: mdp
91          - const: vbif
92
93      clocks:
94        items:
95          - description: Display hf axi clock
96          - description: Display ahb clock
97          - description: Display rotator clock
98          - description: Display lut clock
99          - description: Display core clock
100          - description: Display vsync clock
101
102      clock-names:
103        items:
104          - const: bus
105          - const: iface
106          - const: rot
107          - const: lut
108          - const: core
109          - const: vsync
110
111      interrupts:
112        maxItems: 1
113
114      power-domains:
115        maxItems: 1
116
117      operating-points-v2: true
118      opp-table:
119        type: object
120
121      ports:
122        $ref: /schemas/graph.yaml#/properties/ports
123        description: |
124          Contains the list of output ports from DPU device. These ports
125          connect to interfaces that are external to the DPU hardware,
126          such as DSI, DP etc. Each output port contains an endpoint that
127          describes how it is connected to an external interface.
128
129        properties:
130          port@0:
131            $ref: /schemas/graph.yaml#/properties/port
132            description: DPU_INTF1 (DSI1)
133
134          port@2:
135            $ref: /schemas/graph.yaml#/properties/port
136            description: DPU_INTF0 (DP)
137
138        required:
139          - port@0
140
141    required:
142      - compatible
143      - reg
144      - reg-names
145      - clocks
146      - interrupts
147      - power-domains
148      - operating-points-v2
149      - ports
150
151required:
152  - compatible
153  - reg
154  - reg-names
155  - power-domains
156  - clocks
157  - interrupts
158  - interrupt-controller
159  - iommus
160  - ranges
161
162additionalProperties: false
163
164examples:
165  - |
166    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
167    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
168    #include <dt-bindings/interrupt-controller/arm-gic.h>
169    #include <dt-bindings/interconnect/qcom,sdm845.h>
170    #include <dt-bindings/power/qcom-rpmpd.h>
171
172    display-subsystem@ae00000 {
173         #address-cells = <1>;
174         #size-cells = <1>;
175         compatible = "qcom,sc7180-mdss";
176         reg = <0xae00000 0x1000>;
177         reg-names = "mdss";
178         power-domains = <&dispcc MDSS_GDSC>;
179         clocks = <&gcc GCC_DISP_AHB_CLK>,
180                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
181                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
182         clock-names = "iface", "ahb", "core";
183
184         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
185         interrupt-controller;
186         #interrupt-cells = <1>;
187
188         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
189         interconnect-names = "mdp0-mem";
190
191         iommus = <&apps_smmu 0x800 0x2>;
192         ranges;
193
194         display-controller@ae01000 {
195                   compatible = "qcom,sc7180-dpu";
196                   reg = <0x0ae01000 0x8f000>,
197                         <0x0aeb0000 0x2008>;
198
199                   reg-names = "mdp", "vbif";
200
201                   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
202                            <&dispcc DISP_CC_MDSS_AHB_CLK>,
203                            <&dispcc DISP_CC_MDSS_ROT_CLK>,
204                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
205                            <&dispcc DISP_CC_MDSS_MDP_CLK>,
206                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
207                   clock-names = "bus", "iface", "rot", "lut", "core",
208                                 "vsync";
209
210                   interrupt-parent = <&mdss>;
211                   interrupts = <0>;
212                   power-domains = <&rpmhpd SC7180_CX>;
213                   operating-points-v2 = <&mdp_opp_table>;
214
215                   ports {
216                           #address-cells = <1>;
217                           #size-cells = <0>;
218
219                           port@0 {
220                                   reg = <0>;
221                                   dpu_intf1_out: endpoint {
222                                                  remote-endpoint = <&dsi0_in>;
223                                   };
224                           };
225
226                            port@2 {
227                                    reg = <2>;
228                                    dpu_intf0_out: endpoint {
229                                                   remote-endpoint = <&dp_in>;
230                                    };
231                            };
232                   };
233         };
234    };
235...
236