xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sc7180-dp
21          - qcom,sc7280-dp
22          - qcom,sc7280-edp
23          - qcom,sc8180x-dp
24          - qcom,sc8180x-edp
25          - qcom,sc8280xp-dp
26          - qcom,sc8280xp-edp
27          - qcom,sdm845-dp
28          - qcom,sm8350-dp
29      - items:
30          - enum:
31              - qcom,sm8450-dp
32              - qcom,sm8550-dp
33          - const: qcom,sm8350-dp
34
35  reg:
36    minItems: 4
37    items:
38      - description: ahb register block
39      - description: aux register block
40      - description: link register block
41      - description: p0 register block
42      - description: p1 register block
43
44  interrupts:
45    maxItems: 1
46
47  clocks:
48    items:
49      - description: AHB clock to enable register access
50      - description: Display Port AUX clock
51      - description: Display Port Link clock
52      - description: Link interface clock between DP and PHY
53      - description: Display Port Pixel clock
54
55  clock-names:
56    items:
57      - const: core_iface
58      - const: core_aux
59      - const: ctrl_link
60      - const: ctrl_link_iface
61      - const: stream_pixel
62
63  assigned-clocks:
64    items:
65      - description: link clock source
66      - description: pixel clock source
67
68  assigned-clock-parents:
69    items:
70      - description: phy 0 parent
71      - description: phy 1 parent
72
73  phys:
74    maxItems: 1
75
76  phy-names:
77    items:
78      - const: dp
79
80  operating-points-v2: true
81
82  opp-table: true
83
84  power-domains:
85    maxItems: 1
86
87  aux-bus:
88    $ref: /schemas/display/dp-aux-bus.yaml#
89
90  data-lanes:
91    $ref: /schemas/types.yaml#/definitions/uint32-array
92    deprecated: true
93    minItems: 1
94    maxItems: 4
95    items:
96      maximum: 3
97
98  "#sound-dai-cells":
99    const: 0
100
101  vdda-0p9-supply:
102    deprecated: true
103  vdda-1p2-supply:
104    deprecated: true
105
106  ports:
107    $ref: /schemas/graph.yaml#/properties/ports
108    properties:
109      port@0:
110        $ref: /schemas/graph.yaml#/properties/port
111        description: Input endpoint of the controller
112
113      port@1:
114        $ref: /schemas/graph.yaml#/$defs/port-base
115        description: Output endpoint of the controller
116        properties:
117          endpoint:
118            $ref: /schemas/media/video-interfaces.yaml#
119            unevaluatedProperties: false
120            properties:
121              data-lanes:
122                minItems: 1
123                maxItems: 4
124                items:
125                  enum: [ 0, 1, 2, 3 ]
126
127              link-frequencies:
128                minItems: 1
129                maxItems: 4
130                items:
131                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
132
133    required:
134      - port@0
135      - port@1
136
137required:
138  - compatible
139  - reg
140  - interrupts
141  - clocks
142  - clock-names
143  - phys
144  - phy-names
145  - power-domains
146  - ports
147
148allOf:
149  # AUX BUS does not exist on DP controllers
150  # Audio output also is present only on DP output
151  # p1 regions is present on DP, but not on eDP
152  - if:
153      properties:
154        compatible:
155          contains:
156            enum:
157              - qcom,sc7280-edp
158              - qcom,sc8180x-edp
159              - qcom,sc8280xp-edp
160    then:
161      properties:
162        "#sound-dai-cells": false
163    else:
164      properties:
165        aux-bus: false
166        reg:
167          minItems: 5
168      required:
169        - "#sound-dai-cells"
170
171additionalProperties: false
172
173examples:
174  - |
175    #include <dt-bindings/interrupt-controller/arm-gic.h>
176    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
177    #include <dt-bindings/power/qcom-rpmpd.h>
178
179    displayport-controller@ae90000 {
180        compatible = "qcom,sc7180-dp";
181        reg = <0xae90000 0x200>,
182              <0xae90200 0x200>,
183              <0xae90400 0xc00>,
184              <0xae91000 0x400>,
185              <0xae91400 0x400>;
186        interrupt-parent = <&mdss>;
187        interrupts = <12>;
188        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
189                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
190                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
191                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
192                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
193        clock-names = "core_iface", "core_aux",
194                      "ctrl_link",
195                      "ctrl_link_iface", "stream_pixel";
196
197        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
198                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
199
200        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
201
202        phys = <&dp_phy>;
203        phy-names = "dp";
204
205        #sound-dai-cells = <0>;
206
207        power-domains = <&rpmhpd SC7180_CX>;
208
209        ports {
210            #address-cells = <1>;
211            #size-cells = <0>;
212
213            port@0 {
214                reg = <0>;
215                endpoint {
216                    remote-endpoint = <&dpu_intf0_out>;
217                };
218            };
219
220            port@1 {
221                reg = <1>;
222                endpoint {
223                    remote-endpoint = <&typec>;
224                    data-lanes = <0 1>;
225                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
226                };
227            };
228        };
229    };
230...
231