xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml (revision ebacd8013fe5f7fdf9f6a5b286f6680dd2891036) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc7180-dp
20      - qcom,sc7280-dp
21      - qcom,sc7280-edp
22      - qcom,sc8180x-dp
23      - qcom,sc8180x-edp
24      - qcom,sm8350-dp
25
26  reg:
27    items:
28      - description: ahb register block
29      - description: aux register block
30      - description: link register block
31      - description: p0 register block
32      - description: p1 register block
33
34  interrupts:
35    maxItems: 1
36
37  clocks:
38    items:
39      - description: AHB clock to enable register access
40      - description: Display Port AUX clock
41      - description: Display Port Link clock
42      - description: Link interface clock between DP and PHY
43      - description: Display Port Pixel clock
44
45  clock-names:
46    items:
47      - const: core_iface
48      - const: core_aux
49      - const: ctrl_link
50      - const: ctrl_link_iface
51      - const: stream_pixel
52
53  assigned-clocks:
54    items:
55      - description: link clock source
56      - description: pixel clock source
57
58  assigned-clock-parents:
59    items:
60      - description: phy 0 parent
61      - description: phy 1 parent
62
63  phys:
64    maxItems: 1
65
66  phy-names:
67    items:
68      - const: dp
69
70  operating-points-v2:
71    maxItems: 1
72
73  power-domains:
74    maxItems: 1
75
76  "#sound-dai-cells":
77    const: 0
78
79  vdda-0p9-supply: true
80  vdda-1p2-supply: true
81
82  ports:
83    $ref: /schemas/graph.yaml#/properties/ports
84    properties:
85      port@0:
86        $ref: /schemas/graph.yaml#/properties/port
87        description: Input endpoint of the controller
88
89      port@1:
90        $ref: /schemas/graph.yaml#/properties/port
91        description: Output endpoint of the controller
92
93required:
94  - compatible
95  - reg
96  - interrupts
97  - clocks
98  - clock-names
99  - phys
100  - phy-names
101  - "#sound-dai-cells"
102  - power-domains
103  - ports
104
105additionalProperties: false
106
107examples:
108  - |
109    #include <dt-bindings/interrupt-controller/arm-gic.h>
110    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
111    #include <dt-bindings/power/qcom-rpmpd.h>
112
113    displayport-controller@ae90000 {
114        compatible = "qcom,sc7180-dp";
115        reg = <0xae90000 0x200>,
116              <0xae90200 0x200>,
117              <0xae90400 0xc00>,
118              <0xae91000 0x400>,
119              <0xae91400 0x400>;
120        interrupt-parent = <&mdss>;
121        interrupts = <12>;
122        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
123                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
124                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
125                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
126                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
127        clock-names = "core_iface", "core_aux",
128                      "ctrl_link",
129                      "ctrl_link_iface", "stream_pixel";
130
131        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
132                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
133
134        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
135
136        phys = <&dp_phy>;
137        phy-names = "dp";
138
139        #sound-dai-cells = <0>;
140
141        power-domains = <&rpmhpd SC7180_CX>;
142
143        vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
144        vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
145
146        ports {
147            #address-cells = <1>;
148            #size-cells = <0>;
149
150            port@0 {
151                reg = <0>;
152                endpoint {
153                    remote-endpoint = <&dpu_intf0_out>;
154                };
155            };
156
157            port@1 {
158                reg = <1>;
159                endpoint {
160                    remote-endpoint = <&typec>;
161                };
162            };
163        };
164    };
165...
166