xref: /freebsd/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,split.yaml (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display split
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display split, namely SPLIT, is used to split stream to two
15  encoders.
16  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt8173-disp-split
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  power-domains:
34    description: A phandle and PM domain specifier as defined by bindings of
35      the power controller specified by phandle. See
36      Documentation/devicetree/bindings/power/power-domain.yaml for details.
37
38  clocks:
39    items:
40      - description: SPLIT Clock
41
42required:
43  - compatible
44  - reg
45  - power-domains
46  - clocks
47
48additionalProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/clock/mt8173-clk.h>
53    #include <dt-bindings/power/mt8173-power.h>
54
55    soc {
56        #address-cells = <2>;
57        #size-cells = <2>;
58
59        split0: split@14018000 {
60            compatible = "mediatek,mt8173-disp-split";
61            reg = <0 0x14018000 0 0x1000>;
62            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
63            clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
64        };
65    };
66